[v5,15/31] target/arm: Enforce word alignment for LDRD/STRD

Message ID	20210419202257.161730-16-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH v5 15/31] target/arm: Enforce word alignment for LDRD/STRD Date: Mon, 19 Apr 2021 13:22:41 -0700 Message-Id: <20210419202257.161730-16-richard.henderson@linaro.org> In-Reply-To: <20210419202257.161730-1-richard.henderson@linaro.org> References: <20210419202257.161730-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: enforce alignment \| expand [v5,00/31] target/arm: enforce alignment [v5,01/31] target/arm: Fix decode of align in VLDST_single [v5,02/31] target/arm: Rename TBFLAG_A32, SCTLR_B [v5,03/31] target/arm: Rename TBFLAG_ANY, PSTATE_SS [v5,04/31] target/arm: Add wrapper macros for accessing tbflags [v5,05/31] target/arm: Introduce CPUARMTBFlags [v5,06/31] target/arm: Move mode specific TB flags to tb->cs_base [v5,07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly [v5,08/31] target/arm: Move TBFLAG_AM32 bits to the top [v5,09/31] target/arm: Move TBFLAG_ANY bits to the bottom [v5,10/31] target/arm: Add ALIGN_MEM to TBFLAG_ANY [v5,11/31] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness [v5,12/31] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 [v5,13/31] target/arm: Fix SCTLR_B test for TCGv_i64 load/store [v5,14/31] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness [v5,15/31] target/arm: Enforce word alignment for LDRD/STRD [v5,16/31] target/arm: Enforce alignment for LDA/LDAH/STL/STLH [v5,17/31] target/arm: Enforce alignment for LDM/STM [v5,18/31] target/arm: Enforce alignment for RFE [v5,19/31] target/arm: Enforce alignment for SRS [v5,20/31] target/arm: Enforce alignment for VLDM/VSTM [v5,21/31] target/arm: Enforce alignment for VLDR/VSTR [v5,22/31] target/arm: Enforce alignment for VLDn (all lanes) [v5,23/31] target/arm: Enforce alignment for VLDn/VSTn (multiple) [v5,24/31] target/arm: Enforce alignment for VLDn/VSTn (single) [v5,25/31] target/arm: Use finalize_memop for aa64 gpr load/store [v5,26/31] target/arm: Use finalize_memop for aa64 fpr load/store [v5,27/31] target/arm: Enforce alignment for aa64 load-acq/store-rel [v5,28/31] target/arm: Use MemOp for size + endian in aa64 vector ld/st [v5,29/31] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) [v5,30/31] target/arm: Enforce alignment for aa64 vector LDn/STn (single) [v5,31/31] target/arm: Enforce alignment for sve LD1R

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20210419202257.161730-16-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v5 15/31] target/arm: Enforce word alignment for LDRD/STRD
Date: Mon, 19 Apr 2021 13:22:41 -0700
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Series

target/arm: enforce alignment | expand

Commit Message

Richard Henderson April 19, 2021, 8:22 p.m. UTC

Buglink: https://bugs.launchpad.net/qemu/+bug/1905356
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

-- 
2.25.1

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6171347d6d..1b0951c45b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6512,13 +6512,13 @@  static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
     addr = op_addr_rr_pre(s, a);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     store_reg(s, a->rt, tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     store_reg(s, a->rt + 1, tmp);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
@@ -6541,13 +6541,13 @@  static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
     addr = op_addr_rr_pre(s, a);
 
     tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     tcg_temp_free_i32(tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
 
     tmp = load_reg(s, a->rt + 1);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     tcg_temp_free_i32(tmp);
 
     op_addr_rr_post(s, a, addr, -4);
@@ -6649,13 +6649,13 @@  static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
     addr = op_addr_ri_pre(s, a);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     store_reg(s, a->rt, tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     store_reg(s, rt2, tmp);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
@@ -6688,13 +6688,13 @@  static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
     addr = op_addr_ri_pre(s, a);
 
     tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     tcg_temp_free_i32(tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
 
     tmp = load_reg(s, rt2);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     tcg_temp_free_i32(tmp);
 
     op_addr_ri_post(s, a, addr, -4);

[v5,15/31] target/arm: Enforce word alignment for LDRD/STRD

Commit Message

Patch