From patchwork Mon Sep 26 19:07:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thomas.abraham@linaro.org X-Patchwork-Id: 4341 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EED6A23F57 for ; Mon, 26 Sep 2011 19:07:34 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id E39CEA1860E for ; Mon, 26 Sep 2011 19:07:34 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id 23so8789249fxe.11 for ; Mon, 26 Sep 2011 12:07:34 -0700 (PDT) Received: by 10.223.63.8 with SMTP id z8mr10957823fah.84.1317064054788; Mon, 26 Sep 2011 12:07:34 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.3.234 with SMTP id f10cs48415laf; Mon, 26 Sep 2011 12:07:34 -0700 (PDT) Received: by 10.236.76.225 with SMTP id b61mr42494319yhe.92.1317064053335; Mon, 26 Sep 2011 12:07:33 -0700 (PDT) Received: from mailout3.samsung.com (mailout3.samsung.com. [203.254.224.33]) by mx.google.com with ESMTP id d68si17483293yhe.84.2011.09.26.12.07.32; Mon, 26 Sep 2011 12:07:33 -0700 (PDT) Received-SPF: neutral (google.com: 203.254.224.33 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=neutral (google.com: 203.254.224.33 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) smtp.mail=thomas.abraham@linaro.org Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Exchange Server 7u4-19.01 64bit (built Sep 7 2010)) with ESMTP id <0LS5001IM94FGF10@mailout3.samsung.com> for patches@linaro.org; Tue, 27 Sep 2011 04:07:31 +0900 (KST) X-AuditID: cbfee61b-b7b7fae000005864-ec-4e80cd7353cc Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (MMPCPMTA) with SMTP id 82.8A.22628.37DC08E4; Tue, 27 Sep 2011 04:07:31 +0900 (KST) Received: from localhost.localdomain ([107.108.73.37]) by mmp2.samsung.com (Oracle Communications Messaging Exchange Server 7u4-19.01 64bit (built Sep 7 2010)) with ESMTPA id <0LS5008Q69489390@mmp2.samsung.com> for patches@linaro.org; Tue, 27 Sep 2011 04:07:31 +0900 (KST) From: Thomas Abraham To: linux-serial@vger.kernel.org, devicetree-discuss@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org, alan@linux.intel.com, grant.likely@secretlab.ca, linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com, ben-linux@fluff.org, patches@linaro.org, Vasily Khoruzhick Subject: [PATCH 2/9] serial: samsung: move handling of fclk/n clock to platform code Date: Tue, 27 Sep 2011 00:37:11 +0530 Message-id: <1317064038-32428-3-git-send-email-thomas.abraham@linaro.org> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1317064038-32428-1-git-send-email-thomas.abraham@linaro.org> References: <1317064038-32428-1-git-send-email-thomas.abraham@linaro.org> X-Brightmail-Tracker: AAAAAA== s3c2440 uses fclk/n (fclk divided by n) clock as one of the possible clocks used to generate the baud rate clock. The divider 'n' in this case can be logically represented outside of the uart controller. This patch creates a new clock by name "fclk_n" for s3c2440 based platforms to represent the fclk/n clock in the platform code. This clock provides a get_rate callback that checks the UCON0/1/2 registers to determine the clock rate. The samsung uart driver would receive the "fclk_n" clock name as one of the possible baud rate clock options and the driver need not determine clock rate of fclk/n. Cc: Ben Dooks Cc: Vasily Khoruzhick Signed-off-by: Thomas Abraham --- arch/arm/mach-s3c2440/clock.c | 37 +++++++++++++++++++++++++++++++++++ arch/arm/mach-s3c2440/mach-rx1950.c | 4 +- arch/arm/mach-s3c2440/mach-rx3715.c | 4 +- drivers/tty/serial/s3c2440.c | 33 ++---------------------------- drivers/tty/serial/samsung.c | 21 ------------------- 5 files changed, 44 insertions(+), 55 deletions(-) diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c index f9e6bda..f85853c 100644 --- a/arch/arm/mach-s3c2440/clock.c +++ b/arch/arm/mach-s3c2440/clock.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -43,6 +44,7 @@ #include #include +#include /* S3C2440 extended clock support */ @@ -108,6 +110,40 @@ static struct clk s3c2440_clk_ac97 = { .ctrlbit = S3C2440_CLKCON_CAMERA, }; +static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) +{ + unsigned long ucon0, ucon1, ucon2, divisor; + + /* the fun of calculating the uart divisors on the s3c2440 */ + ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON); + ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON); + ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON); + + ucon0 &= S3C2440_UCON0_DIVMASK; + ucon1 &= S3C2440_UCON1_DIVMASK; + ucon2 &= S3C2440_UCON2_DIVMASK; + + if (ucon0 != 0) + divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6; + else if (ucon1 != 0) + divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21; + else if (ucon2 != 0) + divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36; + else + /* manual calims 44, seems to be 9 */ + divisor = 9; + + return clk_get_rate(clk->parent) / divisor; +} + +static struct clk s3c2440_clk_fclk_n = { + .name = "fclk_n", + .parent = &clk_f, + .ops = &(struct clk_ops) { + .get_rate = s3c2440_fclk_n_getrate, + }, +}; + static int s3c2440_clk_add(struct sys_device *sysdev) { struct clk *clock_upll; @@ -126,6 +162,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev) s3c2440_clk_cam.parent = clock_h; s3c2440_clk_ac97.parent = clock_p; s3c2440_clk_cam_upll.parent = clock_upll; + s3c24xx_register_clock(&s3c2440_clk_fclk_n); s3c24xx_register_clock(&s3c2440_clk_ac97); s3c24xx_register_clock(&s3c2440_clk_cam); diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index 27ea950..9528b37 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -69,8 +69,8 @@ static struct map_desc rx1950_iodesc[] __initdata = { static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = { [0] = { - .name = "fclk", - .divisor = 0x0a, + .name = "fclk_n", + .divisor = 1, .min_baud = 0, .max_baud = 0, }, diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index 1472b1a..a88247e 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -70,8 +70,8 @@ static struct map_desc rx3715_iodesc[] __initdata = { static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = { [0] = { - .name = "fclk", - .divisor = 0, + .name = "fclk_n", + .divisor = 1, .min_baud = 0, .max_baud = 0, } diff --git a/drivers/tty/serial/s3c2440.c b/drivers/tty/serial/s3c2440.c index 1d0c324..4498828 100644 --- a/drivers/tty/serial/s3c2440.c +++ b/drivers/tty/serial/s3c2440.c @@ -39,7 +39,7 @@ static int s3c2440_serial_setsource(struct uart_port *port, ucon |= S3C2440_UCON_UCLK; else if (strcmp(clk->name, "pclk") == 0) ucon |= S3C2440_UCON_PCLK; - else if (strcmp(clk->name, "fclk") == 0) + else if (strcmp(clk->name, "fclk_n") == 0) ucon |= S3C2440_UCON_FCLK; else { printk(KERN_ERR "unknown clock source %s\n", clk->name); @@ -55,7 +55,6 @@ static int s3c2440_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *clk) { unsigned long ucon = rd_regl(port, S3C2410_UCON); - unsigned long ucon0, ucon1, ucon2; switch (ucon & S3C2440_UCON_CLKMASK) { case S3C2440_UCON_UCLK: @@ -70,34 +69,8 @@ static int s3c2440_serial_getsource(struct uart_port *port, break; case S3C2440_UCON_FCLK: - /* the fun of calculating the uart divisors on - * the s3c2440 */ - - ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON); - ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON); - ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON); - - printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2); - - ucon0 &= S3C2440_UCON0_DIVMASK; - ucon1 &= S3C2440_UCON1_DIVMASK; - ucon2 &= S3C2440_UCON2_DIVMASK; - - if (ucon0 != 0) { - clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT; - clk->divisor += 6; - } else if (ucon1 != 0) { - clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT; - clk->divisor += 21; - } else if (ucon2 != 0) { - clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT; - clk->divisor += 36; - } else { - /* manual calims 44, seems to be 9 */ - clk->divisor = 9; - } - - clk->name = "fclk"; + clk->divisor = 1; + clk->name = "fclk_n"; break; } diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 51cfb9f..fc242b2 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -649,27 +649,6 @@ static unsigned int s3c24xx_serial_getclk(struct uart_port *port, if (cfg->clocks_size == 0) clkp = &tmp_clksrc; - /* check to see if we're sourcing fclk, and if so we're - * going to have to update the clock source - */ - - if (strcmp(clkp->name, "fclk") == 0) { - struct s3c24xx_uart_clksrc src; - - s3c24xx_serial_getsource(port, &src); - - /* check that the port already using fclk, and if - * not, then re-select fclk - */ - - if (strcmp(src.name, clkp->name) == 0) { - s3c24xx_serial_setsource(port, clkp); - s3c24xx_serial_getsource(port, &src); - } - - clkp->divisor = src.divisor; - } - s3c24xx_serial_calcbaud(res, port, clkp, baud); best = res; resptr = best + 1;