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[209.132.180.131]) by mx.google.com with ESMTPS id fx11si2366930pdb.63.2015.02.03.04.48.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 03 Feb 2015 04:48:17 -0800 (PST) Received-SPF: pass (google.com: domain of gdb-patches-return-119535-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 566 invoked by alias); 3 Feb 2015 12:47:48 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Subscribe: List-Archive: List-Post: , List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 551 invoked by uid 89); 3 Feb 2015 12:47:46 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_SORBS_WEB, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f173.google.com Received: from mail-wi0-f173.google.com (HELO mail-wi0-f173.google.com) (209.85.212.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 03 Feb 2015 12:47:45 +0000 Received: by mail-wi0-f173.google.com with SMTP id r20so24012201wiv.0 for ; Tue, 03 Feb 2015 04:47:41 -0800 (PST) X-Received: by 10.180.73.84 with SMTP id j20mr33925827wiv.43.1422967661580; Tue, 03 Feb 2015 04:47:41 -0800 (PST) Received: from localhost.localdomain ([182.178.186.12]) by mx.google.com with ESMTPSA id hl1sm32503745wjc.18.2015.02.03.04.47.40 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Feb 2015 04:47:40 -0800 (PST) From: Omair Javaid To: gdb-patches@sourceware.org Subject: [PATCH] ARM gdb record-replay bug fixes Date: Tue, 3 Feb 2015 17:47:29 +0500 Message-Id: <1422967649-17436-1-git-send-email-omair.javaid@linaro.org> X-IsSubscribed: yes X-Original-Sender: omair.javaid@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::231 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@sourceware.org X-Google-Group-Id: 836684582541 This patch provides fixes for some gdb record-replay related testsuite failures on arm. The patch fixes instruction decoding errors in vector data transfer and extension register load/store instructions. This patch has been tested in remote/native mode on armv7 hardware and fixes failures in gdb.record gdb.mi testsuites. Fixes around 40 tests overall. gdb: 2015-02-03 Omair Javaid * aarch64-tdep.c (arm_record_vdata_transfer_insn): Correct floating point register numbers handling. (arm_record_exreg_ld_st_insn): Fix offset calculation, memory recording and floating point register numbers handling. --- gdb/arm-tdep.c | 67 ++++++++++++++++++++++++++++------------------------------ 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 8e9552a..5efc3ea 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11943,7 +11943,6 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; uint32_t record_buf[4]; - const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); reg_t = bits (arm_insn_r->arm_insn, 12, 15); reg_v = bits (arm_insn_r->arm_insn, 21, 23); bits_a = bits (arm_insn_r->arm_insn, 21, 23); @@ -11961,12 +11960,7 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) /* Handle VMOV instruction. */ if (bits_a == 0x00) { - if (bit (arm_insn_r->arm_insn, 20)) - record_buf[0] = reg_t; - else - record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | - (reg_v << 1)); - + record_buf[0] = reg_t; arm_insn_r->reg_rec_count = 1; } /* Handle VMRS instruction. */ @@ -11984,12 +11978,9 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) /* Handle VMOV instruction. */ if (bits_a == 0x00) { - if (bit (arm_insn_r->arm_insn, 20)) - record_buf[0] = reg_t; - else - record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | - (reg_v << 1)); - + uint32_t reg_single; + reg_single = bit (arm_insn_r->arm_insn, 7) | (reg_v << 1); + record_buf[0] = ARM_D0_REGNUM + reg_single / 2; arm_insn_r->reg_rec_count = 1; } /* Handle VMSR instruction. */ @@ -12042,7 +12033,6 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) ULONGEST u_regval = 0; struct regcache *reg_cache = arm_insn_r->regcache; - const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); opcode = bits (arm_insn_r->arm_insn, 20, 24); single_reg = bit (arm_insn_r->arm_insn, 8); @@ -12064,9 +12054,17 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) if (!single_reg) { - record_buf[0] = num_regs + reg_m; - record_buf[1] = num_regs + reg_m + 1; - arm_insn_r->reg_rec_count = 2; + if (reg_m & 0x01) + { + record_buf[0] = ARM_D0_REGNUM + reg_m / 2; + record_buf[1] = ARM_D0_REGNUM + (reg_m + 1) / 2; + arm_insn_r->reg_rec_count = 2; + } + else + { + record_buf[0] = ARM_D0_REGNUM + reg_m / 2; + arm_insn_r->reg_rec_count = 1; + } } else { @@ -12085,7 +12083,7 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) reg_rn = bits (arm_insn_r->arm_insn, 16, 19); regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); - imm_off32 = imm_off8 << 24; + imm_off32 = imm_off8 << 2; memory_count = imm_off8; if (bit (arm_insn_r->arm_insn, 23)) @@ -12103,19 +12101,17 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) { if (!single_reg) { - record_buf_mem[memory_index] = start_address; - record_buf_mem[memory_index + 1] = 4; + record_buf_mem[memory_index++] = 4; + record_buf_mem[memory_index++] = start_address; start_address = start_address + 4; - memory_index = memory_index + 2; } else { - record_buf_mem[memory_index] = start_address; - record_buf_mem[memory_index + 1] = 4; - record_buf_mem[memory_index + 2] = start_address + 4; - record_buf_mem[memory_index + 3] = 4; + record_buf_mem[memory_index++] = 4; + record_buf_mem[memory_index++] = start_address; + record_buf_mem[memory_index++] = 4; + record_buf_mem[memory_index++] = start_address + 4; start_address = start_address + 8; - memory_index = memory_index + 4; } memory_count--; } @@ -12142,7 +12138,8 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) while (reg_count > 0) { if (single_reg) - record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1; + record_buf[reg_index++] = ARM_D0_REGNUM + + (reg_vd + reg_count - 1) / 2; else record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; @@ -12159,7 +12156,7 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) reg_rn = bits (arm_insn_r->arm_insn, 16, 19); regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); - imm_off32 = imm_off8 << 24; + imm_off32 = imm_off8 << 2; memory_count = imm_off8; if (bit (arm_insn_r->arm_insn, 23)) @@ -12169,16 +12166,16 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) if (single_reg) { - record_buf_mem[memory_index] = start_address; - record_buf_mem[memory_index + 1] = 4; + record_buf_mem[memory_index++] = 4; + record_buf_mem[memory_index++] = start_address; arm_insn_r->mem_rec_count = 1; } else { - record_buf_mem[memory_index] = start_address; - record_buf_mem[memory_index + 1] = 4; - record_buf_mem[memory_index + 2] = start_address + 4; - record_buf_mem[memory_index + 3] = 4; + record_buf_mem[memory_index++] = 4; + record_buf_mem[memory_index++] = start_address; + record_buf_mem[memory_index++] = 4; + record_buf_mem[memory_index++] = start_address + 4; arm_insn_r->mem_rec_count = 2; } } @@ -12195,7 +12192,7 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) else { reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); - record_buf[0] = num_regs + reg_vd; + record_buf[0] = ARM_D0_REGNUM + reg_vd / 2; } arm_insn_r->reg_rec_count = 1; }