[v3,1/2] coresight: Adding coresight support for arm64 architecture

Message ID 1423629085-1044-1-git-send-email-mathieu.poirier@linaro.org
State New
Headers show

Commit Message

Mathieu Poirier Feb. 11, 2015, 4:31 a.m.
From: Mathieu Poirier <mathieu.poirier@linaro.org>

Most CoreSight blocks are 64-bit ready.  As such move configuration
entries from "arch/arm/Kconfig.config" to the driver's subdirectory
and source the newly created Kconfig from architecture specific
Kconfig.debug files.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
Change for v3:
  - Separating Kconfig work from compilation warnings fixes.
---
 arch/arm/Kconfig.debug    | 55 +-----------------------------------------
 arch/arm64/Kconfig.debug  |  2 ++
 drivers/coresight/Kconfig | 61 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 64 insertions(+), 54 deletions(-)
 create mode 100644 drivers/coresight/Kconfig

Comments

Mathieu Poirier Feb. 12, 2015, 2:54 a.m. | #1
On 11 February 2015 at 04:36, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Tue, Feb 10, 2015 at 09:31:24PM -0700, mathieu.poirier@linaro.org wrote:
>> From: Mathieu Poirier <mathieu.poirier@linaro.org>
>>
>> Most CoreSight blocks are 64-bit ready.  As such move configuration
>> entries from "arch/arm/Kconfig.config" to the driver's subdirectory
>> and source the newly created Kconfig from architecture specific
>> Kconfig.debug files.
>>
>> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>> ---
>> Change for v3:
>>   - Separating Kconfig work from compilation warnings fixes.
>
> Nitpick: merge the compilation warnings fix first so that we don't get
> them once the Kconfig patch is merged for arm64.
>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>

I intended to merge both patches via my tree and as such ensuring the
Kconfig changes and compilation warnings fix go in at the same time.
Is this fine with you?
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Mathieu Poirier Feb. 13, 2015, 1:46 a.m. | #2
On 12 February 2015 at 02:49, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Wed, Feb 11, 2015 at 07:54:04PM -0700, Mathieu Poirier wrote:
>> On 11 February 2015 at 04:36, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> > On Tue, Feb 10, 2015 at 09:31:24PM -0700, mathieu.poirier@linaro.org wrote:
>> >> From: Mathieu Poirier <mathieu.poirier@linaro.org>
>> >>
>> >> Most CoreSight blocks are 64-bit ready.  As such move configuration
>> >> entries from "arch/arm/Kconfig.config" to the driver's subdirectory
>> >> and source the newly created Kconfig from architecture specific
>> >> Kconfig.debug files.
>> >>
>> >> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>> >> ---
>> >> Change for v3:
>> >>   - Separating Kconfig work from compilation warnings fixes.
>> >
>> > Nitpick: merge the compilation warnings fix first so that we don't get
>> > them once the Kconfig patch is merged for arm64.
>> >
>> > Acked-by: Catalin Marinas <catalin.marinas@arm.com>
>>
>> I intended to merge both patches via my tree and as such ensuring the
>> Kconfig changes and compilation warnings fix go in at the same time.
>> Is this fine with you?
>
> It was more about bisectability. If reordering is problematic (already
> published branch etc.), leave them as they are.

Other than on this mailing list the code hasn't been published.  I
will re-order the patches.

Thanks for the reviews,
Mathieu

>
> --
> Catalin
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Patch hide | download patch | download mbox

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5ddd4906f7a7..4fdbb0c012e6 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1478,59 +1478,6 @@  config DEBUG_SET_MODULE_RONX
 	  against certain classes of kernel exploits.
 	  If in doubt, say "N".
 
-menuconfig CORESIGHT
-	bool "CoreSight Tracing Support"
-	select ARM_AMBA
-	help
-	  This framework provides a kernel interface for the CoreSight debug
-	  and trace drivers to register themselves with. It's intended to build
-	  a topological view of the CoreSight components based on a DT
-	  specification and configure the right serie of components when a
-	  trace source gets enabled.
-
-if CORESIGHT
-config CORESIGHT_LINKS_AND_SINKS
-	bool "CoreSight Link and Sink drivers"
-	help
-	  This enables support for CoreSight link and sink drivers that are
-	  responsible for transporting and collecting the trace data
-	  respectively.  Link and sinks are dynamically aggregated with a trace
-	  entity at run time to form a complete trace path.
-
-config CORESIGHT_LINK_AND_SINK_TMC
-	bool "Coresight generic TMC driver"
-	depends on CORESIGHT_LINKS_AND_SINKS
-	help
-	  This enables support for the Trace Memory Controller driver.  Depending
-	  on its configuration the device can act as a link (embedded trace router
-	  - ETR) or sink (embedded trace FIFO).  The driver complies with the
-	  generic implementation of the component without special enhancement or
-	  added features.
-
-config CORESIGHT_SINK_TPIU
-	bool "Coresight generic TPIU driver"
-	depends on CORESIGHT_LINKS_AND_SINKS
-	help
-	  This enables support for the Trace Port Interface Unit driver, responsible
-	  for bridging the gap between the on-chip coresight components and a trace
-	  port collection engine, typically connected to an external host for use
-	  case capturing more traces than the on-board coresight memory can handle.
-
-config CORESIGHT_SINK_ETBV10
-	bool "Coresight ETBv1.0 driver"
-	depends on CORESIGHT_LINKS_AND_SINKS
-	help
-	  This enables support for the Embedded Trace Buffer version 1.0 driver
-	  that complies with the generic implementation of the component without
-	  special enhancement or added features.
+source "drivers/coresight/Kconfig"
 
-config CORESIGHT_SOURCE_ETM3X
-	bool "CoreSight Embedded Trace Macrocell 3.x driver"
-	select CORESIGHT_LINKS_AND_SINKS
-	help
-	  This driver provides support for processor ETM3.x and PTM1.x modules,
-	  which allows tracing the instructions that a processor is executing
-	  This is primarily useful for instruction level tracing.  Depending
-	  the ETM version data tracing may also be available.
-endif
 endmenu
diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug
index 5fdd6dce8061..650e46056c55 100644
--- a/arch/arm64/Kconfig.debug
+++ b/arch/arm64/Kconfig.debug
@@ -66,4 +66,6 @@  config DEBUG_SET_MODULE_RONX
           against certain classes of kernel exploits.
           If in doubt, say "N".
 
+source "drivers/coresight/Kconfig"
+
 endmenu
diff --git a/drivers/coresight/Kconfig b/drivers/coresight/Kconfig
new file mode 100644
index 000000000000..fc1f1ae7a49d
--- /dev/null
+++ b/drivers/coresight/Kconfig
@@ -0,0 +1,61 @@ 
+#
+# Coresight configuration
+#
+menuconfig CORESIGHT
+	bool "CoreSight Tracing Support"
+	select ARM_AMBA
+	help
+	  This framework provides a kernel interface for the CoreSight debug
+	  and trace drivers to register themselves with. It's intended to build
+	  a topological view of the CoreSight components based on a DT
+	  specification and configure the right serie of components when a
+	  trace source gets enabled.
+
+if CORESIGHT
+config CORESIGHT_LINKS_AND_SINKS
+	bool "CoreSight Link and Sink drivers"
+	help
+	  This enables support for CoreSight link and sink drivers that are
+	  responsible for transporting and collecting the trace data
+	  respectively.  Link and sinks are dynamically aggregated with a trace
+	  entity at run time to form a complete trace path.
+
+config CORESIGHT_LINK_AND_SINK_TMC
+	bool "Coresight generic TMC driver"
+	depends on CORESIGHT_LINKS_AND_SINKS
+	help
+	  This enables support for the Trace Memory Controller driver.
+	  Depending on its configuration the device can act as a link (embedded
+	  trace router - ETR) or sink (embedded trace FIFO).  The driver
+	  complies with the generic implementation of the component without
+	  special enhancement or added features.
+
+config CORESIGHT_SINK_TPIU
+	bool "Coresight generic TPIU driver"
+	depends on CORESIGHT_LINKS_AND_SINKS
+	help
+	  This enables support for the Trace Port Interface Unit driver,
+	  responsible for bridging the gap between the on-chip coresight
+	  components and a trace for bridging the gap between the on-chip
+	  coresight components and a trace port collection engine, typically
+	  connected to an external host for use case capturing more traces than
+	  the on-board coresight memory can handle.
+
+config CORESIGHT_SINK_ETBV10
+	bool "Coresight ETBv1.0 driver"
+	depends on CORESIGHT_LINKS_AND_SINKS
+	help
+	  This enables support for the Embedded Trace Buffer version 1.0 driver
+	  that complies with the generic implementation of the component without
+	  special enhancement or added features.
+
+config CORESIGHT_SOURCE_ETM3X
+	bool "CoreSight Embedded Trace Macrocell 3.x driver"
+	depends on !ARM64
+	select CORESIGHT_LINKS_AND_SINKS
+	help
+	  This driver provides support for processor ETM3.x and PTM1.x modules,
+	  which allows tracing the instructions that a processor is executing
+	  This is primarily useful for instruction level tracing.  Depending
+	  the ETM version data tracing may also be available.
+endif