diff mbox series

[v2,2/6] mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode

Message ID 20210531181757.19458-3-p.yadav@ti.com
State Accepted
Commit 63017068a6d991fdf31147c4996cd29bfde61ac2
Headers show
Series [v2,1/6] mtd: spi-nor: core: use 2 data bytes for template ops | expand

Commit Message

Pratyush Yadav May 31, 2021, 6:17 p.m. UTC
The Octal DTR configuration is stored in the CFR5V register. This
register is 1 byte wide. But 1 byte long transactions are not allowed in
8D-8D-8D mode. Since the next byte address does not contain any
register, it is safe to write any value to it. Write a 0 to it.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---

(no changes since v1)

 drivers/mtd/spi-nor/spansion.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

Comments

Michael Walle June 1, 2021, 12:47 p.m. UTC | #1
Am 2021-05-31 20:17, schrieb Pratyush Yadav:
> The Octal DTR configuration is stored in the CFR5V register. This

> register is 1 byte wide. But 1 byte long transactions are not allowed 

> in

> 8D-8D-8D mode. Since the next byte address does not contain any

> register, it is safe to write any value to it. Write a 0 to it.

> 

> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>

> ---


Can't say much, because there is no public datasheet, is there?

But looks sane. Same for patch 3/6.
Pratyush Yadav June 2, 2021, 7:42 a.m. UTC | #2
On 01/06/21 02:47PM, Michael Walle wrote:
> Am 2021-05-31 20:17, schrieb Pratyush Yadav:

> > The Octal DTR configuration is stored in the CFR5V register. This

> > register is 1 byte wide. But 1 byte long transactions are not allowed in

> > 8D-8D-8D mode. Since the next byte address does not contain any

> > register, it is safe to write any value to it. Write a 0 to it.

> > 

> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>

> > ---

> 

> Can't say much, because there is no public datasheet, is there?


https://www.cypress.com/file/513996/download

> 

> But looks sane. Same for patch 3/6.


-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.
Tudor Ambarus Dec. 23, 2021, 1:06 p.m. UTC | #3
On 5/31/21 9:17 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> The Octal DTR configuration is stored in the CFR5V register. This
> register is 1 byte wide. But 1 byte long transactions are not allowed in
> 8D-8D-8D mode. Since the next byte address does not contain any
> register, it is safe to write any value to it. Write a 0 to it.
> 
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> ---
> 
> (no changes since v1)
> 
>  drivers/mtd/spi-nor/spansion.c | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
> index ee82dcd75310..e6bf5c9eee6a 100644
> --- a/drivers/mtd/spi-nor/spansion.c
> +++ b/drivers/mtd/spi-nor/spansion.c
> @@ -65,10 +65,18 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
>         if (ret)
>                 return ret;
> 
> -       if (enable)
> -               *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
> -       else
> -               *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
> +       if (enable) {
> +               buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
> +       } else {
> +               /*
> +                * The register is 1-byte wide, but 1-byte transactions are not
> +                * allowed in 8D-8D-8D mode. Since there is no register at the
> +                * next location, just initialize the value to 0 and let the
> +                * transaction go on.
> +                */
> +               buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
> +               buf[1] = 0;

how about writing 0xff instead?

> +       }
> 
>         op = (struct spi_mem_op)
>                 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
> @@ -76,7 +84,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
>                                            SPINOR_REG_CYPRESS_CFR5V,
>                                            1),
>                            SPI_MEM_OP_NO_DUMMY,
> -                          SPI_MEM_OP_DATA_OUT(1, buf, 1));
> +                          SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
> 
>         if (!enable)
>                 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
> --
> 2.30.0
>
Tudor Ambarus Dec. 23, 2021, 1:11 p.m. UTC | #4
On 12/23/21 3:06 PM, Tudor Ambarus wrote:
> On 5/31/21 9:17 PM, Pratyush Yadav wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> The Octal DTR configuration is stored in the CFR5V register. This
>> register is 1 byte wide. But 1 byte long transactions are not allowed in
>> 8D-8D-8D mode. Since the next byte address does not contain any
>> register, it is safe to write any value to it. Write a 0 to it.
>>
>> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
>> ---
>>
>> (no changes since v1)
>>
>>  drivers/mtd/spi-nor/spansion.c | 18 +++++++++++++-----
>>  1 file changed, 13 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
>> index ee82dcd75310..e6bf5c9eee6a 100644
>> --- a/drivers/mtd/spi-nor/spansion.c
>> +++ b/drivers/mtd/spi-nor/spansion.c
>> @@ -65,10 +65,18 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
>>         if (ret)
>>                 return ret;
>>
>> -       if (enable)
>> -               *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
>> -       else
>> -               *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
>> +       if (enable) {
>> +               buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
>> +       } else {
>> +               /*
>> +                * The register is 1-byte wide, but 1-byte transactions are not
>> +                * allowed in 8D-8D-8D mode. Since there is no register at the
>> +                * next location, just initialize the value to 0 and let the
>> +                * transaction go on.
>> +                */
>> +               buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
>> +               buf[1] = 0;
> 
> how about writing 0xff instead?

patches 1, 2 and 3 look fine, except for this comment. Would you resend them, or you want
me to do the change locally when applying? Send me an updated comment if so.
> 
>> +       }
>>
>>         op = (struct spi_mem_op)
>>                 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
>> @@ -76,7 +84,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
>>                                            SPINOR_REG_CYPRESS_CFR5V,
>>                                            1),
>>                            SPI_MEM_OP_NO_DUMMY,
>> -                          SPI_MEM_OP_DATA_OUT(1, buf, 1));
>> +                          SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
>>
>>         if (!enable)
>>                 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
>> --
>> 2.30.0
>>
>
Tudor Ambarus Dec. 23, 2021, 1:24 p.m. UTC | #5
On 12/23/21 3:06 PM, Tudor.Ambarus@microchip.com wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 5/31/21 9:17 PM, Pratyush Yadav wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> The Octal DTR configuration is stored in the CFR5V register. This
>> register is 1 byte wide. But 1 byte long transactions are not allowed in
>> 8D-8D-8D mode. Since the next byte address does not contain any
>> register, it is safe to write any value to it. Write a 0 to it.
>>
>> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
>> ---
>>
>> (no changes since v1)
>>
>>  drivers/mtd/spi-nor/spansion.c | 18 +++++++++++++-----
>>  1 file changed, 13 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
>> index ee82dcd75310..e6bf5c9eee6a 100644
>> --- a/drivers/mtd/spi-nor/spansion.c
>> +++ b/drivers/mtd/spi-nor/spansion.c
>> @@ -65,10 +65,18 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
>>         if (ret)
>>                 return ret;
>>
>> -       if (enable)
>> -               *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
>> -       else
>> -               *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
>> +       if (enable) {
>> +               buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
>> +       } else {
>> +               /*
>> +                * The register is 1-byte wide, but 1-byte transactions are not
>> +                * allowed in 8D-8D-8D mode. Since there is no register at the
>> +                * next location, just initialize the value to 0 and let the
>> +                * transaction go on.
>> +                */
>> +               buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
>> +               buf[1] = 0;
> 
> how about writing 0xff instead?

it doesn't matter, it's a register. Will apply first 3.

> 
>> +       }
>>
>>         op = (struct spi_mem_op)
>>                 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
>> @@ -76,7 +84,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
>>                                            SPINOR_REG_CYPRESS_CFR5V,
>>                                            1),
>>                            SPI_MEM_OP_NO_DUMMY,
>> -                          SPI_MEM_OP_DATA_OUT(1, buf, 1));
>> +                          SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
>>
>>         if (!enable)
>>                 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
>> --
>> 2.30.0
>>
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>
diff mbox series

Patch

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index ee82dcd75310..e6bf5c9eee6a 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -65,10 +65,18 @@  static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
 	if (ret)
 		return ret;
 
-	if (enable)
-		*buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
-	else
-		*buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
+	if (enable) {
+		buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
+	} else {
+		/*
+		 * The register is 1-byte wide, but 1-byte transactions are not
+		 * allowed in 8D-8D-8D mode. Since there is no register at the
+		 * next location, just initialize the value to 0 and let the
+		 * transaction go on.
+		 */
+		buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
+		buf[1] = 0;
+	}
 
 	op = (struct spi_mem_op)
 		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
@@ -76,7 +84,7 @@  static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
 					   SPINOR_REG_CYPRESS_CFR5V,
 					   1),
 			   SPI_MEM_OP_NO_DUMMY,
-			   SPI_MEM_OP_DATA_OUT(1, buf, 1));
+			   SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
 
 	if (!enable)
 		spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);