[26/55] target/arm: Implement MVE VABD

Message ID	20210607165821.9892-27-peter.maydell@linaro.org
State	Superseded
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Series	target/arm: First slice of MVE implementation \| expand [00/55] target/arm: First slice of MVE implementation [01/55] tcg: Introduce tcg_remove_ops_after [02/55] target/arm: Enable FPSCR.QC bit for MVE [03/55] target/arm: Handle VPR semantics in existing code [04/55] target/arm: Add handling for PSR.ECI/ICI [05/55] target/arm: Let vfp_access_check() handle late NOCP checks [06/55] target/arm: Implement MVE LCTP [07/55] target/arm: Implement MVE WLSTP insn [08/55] target/arm: Implement MVE DLSTP [09/55] target/arm: Implement MVE LETP insn [10/55] target/arm: Add framework for MVE decode [11/55] target/arm: Implement MVE VLDR/VSTR (non-widening forms) [12/55] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns [13/55] target/arm: Implement MVE VCLZ [14/55] target/arm: Implement MVE VCLS [15/55] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations [16/55] target/arm: Implement MVE VREV16, VREV32, VREV64 [17/55] target/arm: Implement MVE VMVN (register) [18/55] target/arm: Implement MVE VABS [19/55] target/arm: Implement MVE VNEG [20/55] target/arm: Implement MVE VDUP [21/55] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR [22/55] target/arm: Implement MVE VADD, VSUB, VMUL [23/55] target/arm: Implement MVE VMULH [24/55] target/arm: Implement MVE VRMULH [25/55] target/arm: Implement MVE VMAX, VMIN [26/55] target/arm: Implement MVE VABD [27/55] target/arm: Implement MVE VHADD, VHSUB [28/55] target/arm: Implement MVE VMULL [29/55] target/arm: Implement MVE VMLALDAV [30/55] target/arm: Implement MVE VMLSLDAV [31/55] include/qemu/int128.h: Add function to create Int128 from int64_t [32/55] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH [33/55] target/arm: Implement MVE VADD (scalar) [34/55] target/arm: Implement MVE VSUB, VMUL (scalar) [35/55] target/arm: Implement MVE VHADD, VHSUB (scalar) [36/55] target/arm: Implement MVE VBRSR [37/55] target/arm: Implement MVE VPST [38/55] target/arm: Implement MVE VQADD and VQSUB [39/55] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) [40/55] target/arm: Implement MVE VQDMULL scalar [41/55] target/arm: Implement MVE VQDMULH, VQRDMULH (vector) [42/55] target/arm: Implement MVE VQADD, VQSUB (vector) [43/55] target/arm: Implement MVE VQSHL (vector) [44/55] target/arm: Implement MVE VQRSHL [45/55] target/arm: Implement MVE VSHL insn [46/55] target/arm: Implement MVE VRSHL [47/55] target/arm: Implement MVE VQDMLADH and VQRDMLADH [48/55] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH [49/55] target/arm: Implement MVE VQDMULL (vector) [50/55] target/arm: Implement MVE VRHADD [51/55] target/arm: Implement MVE VADC, VSBC [52/55] target/arm: Implement MVE VCADD [53/55] target/arm: Implement MVE VHCADD [54/55] target/arm: Implement MVE VADDV [55/55] target/arm: Make VMOV scalar <-> gpreg beatwise for MVE

Message ID

20210607165821.9892-27-peter.maydell@linaro.org

State

Superseded

Headers

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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH 26/55] target/arm: Implement MVE VABD
Date: Mon,  7 Jun 2021 17:57:52 +0100
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Series

target/arm: First slice of MVE implementation | expand

Commit Message

Peter Maydell June 7, 2021, 4:57 p.m. UTC

Implement the MVE VABD insn.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper-mve.h    | 7 +++++++
 target/arm/mve.decode      | 3 +++
 target/arm/mve_helper.c    | 5 +++++
 target/arm/translate-mve.c | 2 ++
 4 files changed, 17 insertions(+)

-- 
2.20.1

Comments

Richard Henderson June 8, 2021, 11:39 p.m. UTC | #1

On 6/7/21 9:57 AM, Peter Maydell wrote:
> Implement the MVE VABD insn.

> 

> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>

> ---

>   target/arm/helper-mve.h    | 7 +++++++

>   target/arm/mve.decode      | 3 +++

>   target/arm/mve_helper.c    | 5 +++++

>   target/arm/translate-mve.c | 2 ++

>   4 files changed, 17 insertions(+)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index bc9dcde5dba..bfe2057592f 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -111,3 +111,10 @@  DEF_HELPER_FLAGS_4(mve_vminsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_4(mve_vminub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_4(mve_vminuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_4(mve_vminuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vabdsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vabdsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vabdsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vabdub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vabduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vabduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 42d5504500c..087d3db2a31 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -93,6 +93,9 @@  VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
 VMIN_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op
 VMIN_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op
 
+VABD_S           111 0 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op
+VABD_U           111 1 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op
+
 # Vector miscellaneous
 
 VCLS             1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index f53551c7de5..f026a9969d6 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -410,3 +410,8 @@  DO_2OP_S(vmaxs, DO_MAX)
 DO_2OP_U(vmaxu, DO_MAX)
 DO_2OP_S(vmins, DO_MIN)
 DO_2OP_U(vminu, DO_MIN)
+
+#define DO_ABD(N, M)  ((N) >= (M) ? (N) - (M) : (M) - (N))
+
+DO_2OP_S(vabds, DO_ABD)
+DO_2OP_U(vabdu, DO_ABD)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index c12b0174b82..a732612a86f 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -387,3 +387,5 @@  DO_2OP(VMAX_S, vmaxs)
 DO_2OP(VMAX_U, vmaxu)
 DO_2OP(VMIN_S, vmins)
 DO_2OP(VMIN_U, vminu)
+DO_2OP(VABD_S, vabds)
+DO_2OP(VABD_U, vabdu)

[26/55] target/arm: Implement MVE VABD

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