diff mbox series

[43/55] target/arm: Implement MVE VQSHL (vector)

Message ID 20210607165821.9892-44-peter.maydell@linaro.org
State Superseded
Headers show
Series target/arm: First slice of MVE implementation | expand

Commit Message

Peter Maydell June 7, 2021, 4:58 p.m. UTC 
Implement the MVE VQSHL insn (encoding T4, which is the
vector-shift-by-vector version).

The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from
the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper-mve.h    |  8 +++++
 target/arm/mve.decode      | 12 +++++++
 target/arm/mve_helper.c    | 73 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  2 ++
 4 files changed, 95 insertions(+)

-- 
2.20.1

Comments

Richard Henderson June 9, 2021, 7:26 p.m. UTC | #1 
On 6/7/21 9:58 AM, Peter Maydell wrote:
> Implement the MVE VQSHL insn (encoding T4, which is the

> vector-shift-by-vector version).

> 

> The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from

> the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}.


Ah, from before the sve2 merge, and associated cleanup.
There are now helper functions in vec_internal.h for this.

The decode looks fine.


r~
Peter Maydell June 14, 2021, 11:04 a.m. UTC | #2 
On Wed, 9 Jun 2021 at 20:26, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> On 6/7/21 9:58 AM, Peter Maydell wrote:

> > Implement the MVE VQSHL insn (encoding T4, which is the

> > vector-shift-by-vector version).

> >

> > The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from

> > the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}.

>

> Ah, from before the sve2 merge, and associated cleanup.

> There are now helper functions in vec_internal.h for this.


Ah, that's helpful. Annoyingly, the helper wants to take a
uint32_t* for the "write to this when saturating" argument,
and I have a bool*...

-- PMM
diff mbox series

Patch

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 9801a39a984..352b6a46a5e 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -171,6 +171,14 @@  DEF_HELPER_FLAGS_4(mve_vqsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_4(mve_vqsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_4(mve_vqsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 
+DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vqshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
 DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 80fa647c08f..2c37e265765 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -40,6 +40,15 @@ 
 @2op .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn
 @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
 
+# The _rev suffix indicates that Vn and Vm are reversed. This is
+# the case for shifts. In the Arm ARM these insns are documented
+# with the Vm and Vn fields in their usual places, but in the
+# assembly the operands are listed "backwards", ie in the order
+# Qd, Qm, Qn where other insns use Qd, Qn, Qm. For QEMU we choose
+# to consider Vm and Vn as being in different fields in the insn.
+# This gives us consistency with A64 and Neon.
+@2op_rev .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qn qn=%qm
+
 @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 
@@ -121,6 +130,9 @@  VQADD_U          111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op
 VQSUB_S          111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op
 VQSUB_U          111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op
 
+VQSHL_S          111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
+VQSHL_U          111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
+
 # Vector miscellaneous
 
 VCLS             1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index d3562f80026..7ac41cb1460 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -376,6 +376,18 @@  DO_1OP(vfnegs, 4, uint32_t, H4, DO_FNEG)
         mve_advance_vpt(env);                                           \
     }
 
+/* provide unsigned 2-op helpers for all sizes */
+#define DO_2OP_SAT_U(OP, FN)                    \
+    DO_2OP_SAT(OP##b, 1, uint8_t, H1, FN)       \
+    DO_2OP_SAT(OP##h, 2, uint16_t, H2, FN)      \
+    DO_2OP_SAT(OP##w, 4, uint32_t, H4, FN)
+
+/* provide signed 2-op helpers for all sizes */
+#define DO_2OP_SAT_S(OP, FN)                    \
+    DO_2OP_SAT(OP##b, 1, int8_t, H1, FN)        \
+    DO_2OP_SAT(OP##h, 2, int16_t, H2, FN)       \
+    DO_2OP_SAT(OP##w, 4, int32_t, H4, FN)
+
 #define DO_AND(N, M)  ((N) & (M))
 #define DO_BIC(N, M)  ((N) & ~(M))
 #define DO_ORR(N, M)  ((N) | (M))
@@ -564,6 +576,67 @@  DO_2OP_SAT(vqsubsb, 1, int8_t, H1, DO_SQSUB_B)
 DO_2OP_SAT(vqsubsh, 2, int16_t, H2, DO_SQSUB_H)
 DO_2OP_SAT(vqsubsw, 4, int32_t, H4, DO_SQSUB_W)
 
+#define DO_SQSHL_OP(src1, src2, satp)                           \
+    ({                                                          \
+        int8_t tmp;                                             \
+        typeof(src1) dest;                                      \
+        tmp = (int8_t)src2;                                     \
+        if (tmp >= (ssize_t)sizeof(src1) * 8) {                 \
+            if (src1) {                                         \
+                *satp = true;                                   \
+                dest = (uint32_t)(1 << (sizeof(src1) * 8 - 1)); \
+                if (src1 > 0) {                                 \
+                    dest--;                                     \
+                }                                               \
+            } else {                                            \
+                dest = src1;                                    \
+            }                                                   \
+        } else if (tmp <= -(ssize_t)sizeof(src1) * 8) {         \
+            dest = src1 >> 31;                                  \
+        } else if (tmp < 0) {                                   \
+            dest = src1 >> -tmp;                                \
+        } else {                                                \
+            dest = src1 << tmp;                                 \
+            if ((dest >> tmp) != src1) {                        \
+                *satp = true;                                   \
+                dest = (uint32_t)(1 << (sizeof(src1) * 8 - 1)); \
+                if (src1 > 0) {                                 \
+                    dest--;                                     \
+                }                                               \
+            }                                                   \
+        }                                                       \
+        dest;                                                   \
+    })
+
+#define DO_UQSHL_OP(src1, src2, satp)                   \
+    ({                                                  \
+        int8_t tmp;                                     \
+        typeof(src1) dest;                              \
+        tmp = (int8_t)src2;                             \
+        if (tmp >= (ssize_t)sizeof(src1) * 8) {         \
+            if (src1) {                                 \
+                *satp = true;                           \
+                dest = ~0;                              \
+            } else {                                    \
+                dest = 0;                               \
+            }                                           \
+        } else if (tmp <= -(ssize_t)sizeof(src1) * 8) { \
+            dest = 0;                                   \
+        } else if (tmp < 0) {                           \
+            dest = src1 >> -tmp;                        \
+        } else {                                        \
+            dest = src1 << tmp;                         \
+            if ((dest >> tmp) != src1) {                \
+                *satp = true;                           \
+                dest = ~0;                              \
+            }                                           \
+        }                                               \
+        dest;                                           \
+    })
+
+DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
+DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
+
 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, H, FN)                           \
     void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn,   \
                                 uint32_t rm)                            \
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 957e7e48fab..998f47fb94e 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -421,6 +421,8 @@  DO_2OP(VQADD_S, vqadds)
 DO_2OP(VQADD_U, vqaddu)
 DO_2OP(VQSUB_S, vqsubs)
 DO_2OP(VQSUB_U, vqsubu)
+DO_2OP(VQSHL_S, vqshls)
+DO_2OP(VQSHL_U, vqshlu)
 
 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
                           MVEGenTwoOpScalarFn fn)