From patchwork Mon Oct 10 08:11:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thomas.abraham@linaro.org X-Patchwork-Id: 4581 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id A368B23E51 for ; Mon, 10 Oct 2011 08:10:14 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 91D62A18137 for ; Mon, 10 Oct 2011 08:10:14 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id 5so10409625bke.11 for ; Mon, 10 Oct 2011 01:10:14 -0700 (PDT) Received: by 10.223.92.152 with SMTP id r24mr30719773fam.19.1318234214249; Mon, 10 Oct 2011 01:10:14 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.23.170 with SMTP id n10cs86377laf; Mon, 10 Oct 2011 01:10:14 -0700 (PDT) Received: by 10.150.163.6 with SMTP id l6mr5256746ybe.40.1318234213069; Mon, 10 Oct 2011 01:10:13 -0700 (PDT) Received: from mailout1.samsung.com (mailout1.samsung.com. [203.254.224.24]) by mx.google.com with ESMTP id o3si2882510ybl.33.2011.10.10.01.10.12; Mon, 10 Oct 2011 01:10:13 -0700 (PDT) Received-SPF: neutral (google.com: 203.254.224.24 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=neutral (google.com: 203.254.224.24 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) smtp.mail=thomas.abraham@linaro.org Received: from epcpsbgm1.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Exchange Server 7u4-19.01 64bit (built Sep 7 2010)) with ESMTP id <0LSU00LX6C0WU430@mailout1.samsung.com> for patches@linaro.org; Mon, 10 Oct 2011 17:10:10 +0900 (KST) X-AuditID: cbfee61a-b7cf1ae00000208e-3b-4e92a862ea76 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (MMPCPMTA) with SMTP id 7A.5B.08334.268A29E4; Mon, 10 Oct 2011 17:10:10 +0900 (KST) Received: from localhost.localdomain ([107.108.73.37]) by mmp2.samsung.com (Oracle Communications Messaging Exchange Server 7u4-19.01 64bit (built Sep 7 2010)) with ESMTPA id <0LSU001GXC0LKE30@mmp2.samsung.com> for patches@linaro.org; Mon, 10 Oct 2011 17:10:10 +0900 (KST) From: Thomas Abraham To: devicetree-discuss@lists.ozlabs.org, linux-samsung-soc@vger.kernel.org Cc: grant.likely@secretlab.ca, rob.herring@calxeda.com, kgene.kim@samsung.com, linux-arm-kernel@lists.infradead.org, patches@linaro.org Subject: [PATCH 3/3] ARM: Exynos4: Add support for dt irq specifier to linux virq conversion Date: Mon, 10 Oct 2011 13:41:29 +0530 Message-id: <1318234289-22041-4-git-send-email-thomas.abraham@linaro.org> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1318234289-22041-1-git-send-email-thomas.abraham@linaro.org> References: <1318234289-22041-1-git-send-email-thomas.abraham@linaro.org> X-Brightmail-Tracker: AAAAAA== Add support for conversion of device tree interrupt specifier to linux virq domain for GIC and Interrupt combiner controllers. Signed-off-by: Thomas Abraham --- .../devicetree/bindings/irq/samsung-combiner.txt | 24 ++++++++++ arch/arm/mach-exynos4/cpu.c | 20 ++++++++- arch/arm/mach-exynos4/irq-combiner.c | 45 ++++++++++++++++++++ 3 files changed, 88 insertions(+), 1 deletions(-) create mode 100644 Documentation/devicetree/bindings/irq/samsung-combiner.txt diff --git a/Documentation/devicetree/bindings/irq/samsung-combiner.txt b/Documentation/devicetree/bindings/irq/samsung-combiner.txt new file mode 100644 index 0000000..b7d5c30 --- /dev/null +++ b/Documentation/devicetree/bindings/irq/samsung-combiner.txt @@ -0,0 +1,24 @@ +* Exynos4 Interrupt Combiner Controller + +Samsung's Exynos4 architecture includes a interrupt combiner which +can combine interrupt sources as a group and provide a single +interrupt request for the group. The interrupt request from each +group are connected to a parent interrupt controller, which is GIC +in case of Exynos4. + +Required properties: +- compatible: should be "samsung,exynos4-combiner". +- interrupt-cells: should be <2>. The meaning of the cells are + * First Cell: Combiner Group Number. + * Second Cell: Interrupt within the group. +- reg: Base address and size of interrupt combiner registers. +- interrupt-controller: Identifies the node as an interrupt controller. + +Example: + + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x10440000 0x200>; + }; diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 358624d..776e8d4 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -10,6 +10,8 @@ #include #include +#include +#include #include #include @@ -38,6 +40,8 @@ unsigned int gic_bank_offset __read_mostly; extern int combiner_init(unsigned int combiner_nr, void __iomem *base, unsigned int irq_start); extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); +extern void combiner_init_dt(struct device_node *node, + struct device_node *parent); /* Initial IO mappings */ static struct map_desc exynos4_iodesc[] __initdata = { @@ -229,13 +233,27 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d) (gic_bank_offset * smp_processor_id()); } +#ifdef CONFIG_OF +static const struct of_device_id exynos4_dt_irq_match[] = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, + { .compatible = "samsung,exynos4-combiner", .data = combiner_init_dt, }, + {}, +}; +#endif + void __init exynos4_init_irq(void) { int irq; gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; - gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); +#ifdef CONFIG_OF + if (of_have_populated_dt()) + of_irq_init(exynos4_dt_irq_match); + else +#endif + gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); + gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base; gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base; gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base; diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c index 5a2758a..198bd0d 100644 --- a/arch/arm/mach-exynos4/irq-combiner.c +++ b/arch/arm/mach-exynos4/irq-combiner.c @@ -12,7 +12,12 @@ * published by the Free Software Foundation. */ +#include #include +#include +#include +#include +#include #include @@ -122,3 +127,43 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base, set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } + +#ifdef CONFIG_OF +/* Translate dt irq specifier to linux virq for interrupt combiner controller */ +static int exynos4_irq_domain_combiner_dt_translate(struct irq_domain *d, + struct device_node *controller, + const u32 *intspec, unsigned int intsize, + unsigned long *out_hwirq, unsigned int *out_type) +{ + if (d->of_node != controller) + return -EINVAL; + if (intsize < 2) + return -EINVAL; + + *out_hwirq = COMBINER_IRQ(intspec[0], intspec[1]); + *out_type = IRQ_TYPE_NONE; + return 0; +} + +static struct irq_domain_ops exynos4_irq_domain_combiner_ops = { + .dt_translate = exynos4_irq_domain_combiner_dt_translate, +}; + +void __init combiner_init_dt(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *domain; + + if (WARN(!node, "combiner_init_dt: invalid node in parameter\n")) + return; + + domain = kzalloc(sizeof(*domain), GFP_KERNEL); + if (domain) { + domain->of_node = node; + domain->ops = &exynos4_irq_domain_combiner_ops; + irq_domain_add(domain); + } else { + WARN_ON(1); + } +} +#endif