| Message ID | 46310530171886c6ccf4046518e07510274a506c.1623308843.git.geert+renesas@glider.be |
|---|---|
| State | New |
| Headers | show |
| Series | [v6] dt-bindings: clk: versaclock5: Miscellaneous fixes and improvements: | expand |
Quoting Geert Uytterhoeven (2021-06-10 00:09:40) > - Add missing "additionalProperties: false" for subnodes, to catch > typos in properties, > - Fix property names in example. > > Fixes: 45c940184b501fc6 ("dt-bindings: clk: versaclock5: convert to yaml") > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> > Reviewed-by: Rob Herring <robh@kernel.org> > Acked-by: Stephen Boyd <sboyd@kernel.org> > --- Applied to clk-next
Quoting Geert Uytterhoeven (2021-06-10 00:09:40) > - Add missing "additionalProperties: false" for subnodes, to catch > typos in properties, > - Fix property names in example. > > Fixes: 45c940184b501fc6 ("dt-bindings: clk: versaclock5: convert to yaml") > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> > Reviewed-by: Rob Herring <robh@kernel.org> > Acked-by: Stephen Boyd <sboyd@kernel.org> > --- Actually looks like Rob picked something similar up, so dropped it.
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml index 28675b0b80f1ba53..434212320c9aa7ab 100644 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml @@ -85,6 +85,8 @@ patternProperties: description: The Slew rate control for CMOS single-ended. enum: [ 80, 85, 90, 100 ] + additionalProperties: false + required: - compatible - reg @@ -139,13 +141,13 @@ examples: clock-names = "xin"; OUT1 { - idt,drive-mode = <VC5_CMOSD>; - idt,voltage-microvolts = <1800000>; + idt,mode = <VC5_CMOSD>; + idt,voltage-microvolt = <1800000>; idt,slew-percent = <80>; }; OUT4 { - idt,drive-mode = <VC5_LVDS>; + idt,mode = <VC5_LVDS>; }; }; };
- Add missing "additionalProperties: false" for subnodes, to catch typos in properties, - Fix property names in example. Fixes: 45c940184b501fc6 ("dt-bindings: clk: versaclock5: convert to yaml") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> --- This depends on dt-schema v2021.2.1. v6: - Rebase on top of commit c17611592d9635c4 ("dt-bindings: More removals of type references on common properties"), which already removed unneeded references for "idt,xtal-load-femtofarads" and "idt,slew-percent", v5: - Drop reference for "idt,xtal-load-femtofarads", v4: - Add Reviewed-by, Acked-by, v3: - Drop references for "idt,voltage-microvolt" and "idt,slew-percent", v2: - Settle on "idt,voltage-microvolt", cfr. commit 4b003f5fcadfa2d0 ('clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"'), - Drop reference to clock.yaml, which is already applied unconditionally, - Drop removal of allOf around if condition, as it is unnecessary churn. --- .../devicetree/bindings/clock/idt,versaclock5.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)