From patchwork Wed Mar 18 14:20:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 45956 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f71.google.com (mail-wg0-f71.google.com [74.125.82.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id C6B532153C for ; Wed, 18 Mar 2015 14:21:18 +0000 (UTC) Received: by wggx13 with SMTP id x13sf7490643wgg.0 for ; Wed, 18 Mar 2015 07:21:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=rZZw448PCmDQE/sp5u4Yq8DjscdYcyswieUyD9/S3rk=; b=Ard6Kq5qRSd3DInCquYt89sBU+9HElpkYqZPyUpeGYd4iKFypvMizVAbqFW1pws6CN TwanLmx0DqPt/0f4HpyJ/sFqpidrQ6MAJi9QXAGxZmpmI/qiyahHQ9ZjtBkjssz2eP2E MhYcPs/6QZxAYqqt3n0/Sk7cCJ5RNFggmg9StBhDPhukasntjKiwdDr4v9kOD+0pdwkD hZMQskUkNX4Dnf33U0KRexQYfjrL3Fnhso2zjkBOiPMPWbnXf5aKZ2WQT6Nupwu033GL cEWc6CGXVd941HCYEzdb9JIjWWAbTO+5K2EpCiq3+dGS+zln2PsKPRx4Nf9Pcjb3mggZ lpHg== X-Gm-Message-State: ALoCoQlTntTwisKarVYm6/pe5UDm+Ja9Ht5FOHOX0uE89nYIvfXpK9/kV3XEfZTyhq9EC/KdWq4L X-Received: by 10.180.80.132 with SMTP id r4mr808343wix.4.1426688478056; Wed, 18 Mar 2015 07:21:18 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.180.75 with SMTP id dm11ls167891lac.70.gmail; Wed, 18 Mar 2015 07:21:17 -0700 (PDT) X-Received: by 10.152.21.136 with SMTP id v8mr65154269lae.64.1426688477891; Wed, 18 Mar 2015 07:21:17 -0700 (PDT) Received: from mail-la0-f53.google.com (mail-la0-f53.google.com. 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[82.33.25.72]) by mx.google.com with ESMTPSA id m9sm3355898wiz.24.2015.03.18.07.21.14 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Mar 2015 07:21:15 -0700 (PDT) From: Daniel Thompson To: linux-arm-kernel@lists.infradead.org Cc: Daniel Thompson , Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, patches@linaro.org, linaro-kernel@lists.linaro.org, John Stultz , Sumit Semwal , Marc Zyngier , Andrew Thoelke Subject: [RFC PATCH 3/7] irqchip: gic-v3: Reset BPR during initialization Date: Wed, 18 Mar 2015 14:20:24 +0000 Message-Id: <1426688428-3150-4-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1426688428-3150-1-git-send-email-daniel.thompson@linaro.org> References: <1426688428-3150-1-git-send-email-daniel.thompson@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.thompson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Currently, when running on FVP, CPU 0 boots up with its BPR changed from the reset value. This renders it impossible to (preemptively) prioritize interrupts on CPU 0. This is harmless on normal systems but prevents preemption by NMIs on systems with CONFIG_USE_ICC_SYSREGS_FOR_IRQFLAGS enabled. Many thanks to Andrew Thoelke for suggesting the BPR as having the potential to harm preemption. Suggested-by: Andrew Thoelke Signed-off-by: Daniel Thompson --- drivers/irqchip/irq-gic-v3.c | 13 +++++++++++++ include/linux/irqchip/arm-gic-v3.h | 2 ++ 2 files changed, 15 insertions(+) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index fd8850def1b8..32533650494c 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -120,6 +120,11 @@ static void __maybe_unused gic_write_pmr(u64 val) asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); } +static void __maybe_unused gic_write_bpr1(u64 val) +{ + asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val)); +} + static void __maybe_unused gic_write_ctlr(u64 val) { asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); @@ -383,6 +388,14 @@ static void gic_cpu_sys_reg_init(void) /* Set priority mask register */ gic_write_pmr(DEFAULT_PMR_VALUE); + /* + * On FVP, CPU 0 arrives in the kernel with its BPR changed from the + * reset value (and the value is large enough to prevent pre-emptive + * interrupts from working at all). Writing a zero to BPR restores the + * reset value. + */ + gic_write_bpr1(0); + /* EOI deactivates interrupt too (mode 0) */ gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 781974afff9f..79d6645897e6 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -270,6 +270,8 @@ #define ICH_VMCR_PMR_SHIFT 24 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) +#define ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) +#define ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) #define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) #define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) #define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)