From patchwork Thu Apr 9 08:23:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 46908 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f197.google.com (mail-lb0-f197.google.com [209.85.217.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4E30C21416 for ; Thu, 9 Apr 2015 08:23:30 +0000 (UTC) Received: by lbbrr5 with SMTP id rr5sf22567895lbb.3 for ; Thu, 09 Apr 2015 01:23:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=gTsRxDqQ6/MGZi7gb2QTlIqjrFJiDyHLR72yMPcL8dY=; b=T8tCwODoWqaamVUQRjdvM0I33szT3XASluVKJaxR7Gyq4FT8hUF4Cogw9tfpG/1BUO WgGB5dEPpjeT6XWJRb5mAWmWNu6JI/vbh0k3+DVpGZuzBManx8jd4+J+yO0pPH+Ld85z n4n76JxlRDCOnls2J1Mgt7Ylb0JNLJSaTagR9upV8yKCdiPuYfLvE2OzND0kFGsa1bne DMSS/jEl+ahrSIzy1+/gUfeSAyEdSqkBH0kT9kYS/u4O4wIm/tgtjLzoiiJ3g3V6kojE tkaAjaFOB4dbHSedzkC1lHhZIneUSSU4VnXjuUnFqiVLDJ+KZxbJ/rUYBBWeH+ZD4GkV qE4A== X-Gm-Message-State: ALoCoQn7VNJN9etwBMWxv6V1a0k5jRaNBJp244y4kE20SGCUGDYlEUIW1kZwwEjMsH31jCoQ9cCq X-Received: by 10.113.11.3 with SMTP id ee3mr3530910lbd.9.1428567808877; Thu, 09 Apr 2015 01:23:28 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.206.4 with SMTP id lk4ls260938lac.15.gmail; Thu, 09 Apr 2015 01:23:28 -0700 (PDT) X-Received: by 10.112.160.165 with SMTP id xl5mr27184384lbb.109.1428567808638; Thu, 09 Apr 2015 01:23:28 -0700 (PDT) Received: from mail-la0-f44.google.com (mail-la0-f44.google.com. [209.85.215.44]) by mx.google.com with ESMTPS id ot8si10842320lbb.177.2015.04.09.01.23.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Apr 2015 01:23:28 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) client-ip=209.85.215.44; Received: by layy10 with SMTP id y10so83994104lay.0 for ; Thu, 09 Apr 2015 01:23:28 -0700 (PDT) X-Received: by 10.152.28.5 with SMTP id x5mr3331252lag.112.1428567808545; Thu, 09 Apr 2015 01:23:28 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.67.65 with SMTP id l1csp328608lbt; Thu, 9 Apr 2015 01:23:27 -0700 (PDT) X-Received: by 10.66.101.106 with SMTP id ff10mr55159344pab.103.1428567806752; Thu, 09 Apr 2015 01:23:26 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v16si20039666pbs.220.2015.04.09.01.23.25; Thu, 09 Apr 2015 01:23:26 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751834AbbDIIXY (ORCPT + 5 others); Thu, 9 Apr 2015 04:23:24 -0400 Received: from mail-wg0-f46.google.com ([74.125.82.46]:34279 "EHLO mail-wg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753416AbbDIIXX (ORCPT ); Thu, 9 Apr 2015 04:23:23 -0400 Received: by wgso17 with SMTP id o17so220958wgs.1 for ; Thu, 09 Apr 2015 01:23:21 -0700 (PDT) X-Received: by 10.180.19.134 with SMTP id f6mr4045555wie.35.1428567801876; Thu, 09 Apr 2015 01:23:21 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-145-247-151.as13285.net. [78.145.247.151]) by mx.google.com with ESMTPSA id hn8sm19057236wib.18.2015.04.09.01.23.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Apr 2015 01:23:21 -0700 (PDT) From: Srinivas Kandagatla To: galak@codeaurora.org, linux-arm-msm@vger.kernel.org Cc: bjorn.andersson@sonymobile.com, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Russell King , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, inux-kernel@vger.kernel.org, Rob Clark , Srinivas Kandagatla Subject: [PATCH 05/10] ARM: dts: apq8064: Add MDP support Date: Thu, 9 Apr 2015 09:23:17 +0100 Message-Id: <1428567797-10935-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1428567674-10672-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1428567674-10672-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Rob Clark This patch adds MDP node to APQ8064 dt. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 105 ++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index ea0145f..70e417f 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1,6 +1,7 @@ /dts-v1/; #include "skeleton.dtsi" +#include #include #include #include @@ -108,6 +109,20 @@ }; }; + hdmi_pinctrl: hdmi-pinctrl { + mux1 { + pins = "gpio69", "gpio70", "gpio71"; + function = "hdmi"; + bias-pull-up; + drive-strength = <2>; + }; + mux2 { + pins = "gpio72"; + function = "hdmi"; + bias-pull-down; + drive-strength = <16>; + }; + }; ps_hold: ps_hold { mux { pins = "gpio78"; @@ -251,6 +266,18 @@ }; }; + ext_3p3v: regulator-fixed@1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ext_3p3v"; + regulator-type = "voltage"; + startup-delay-us = <0>; + gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + qcom,ssbi@500000 { compatible = "qcom,ssbi"; reg = <0x00500000 0x1000>; @@ -770,5 +797,83 @@ compatible = "qcom,tcsr-apq8064", "syscon"; reg = <0x1a400000 0x100>; }; + + hdmi: qcom,hdmi-tx@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg-names = "core_physical"; + reg = <0x04a00000 0x1000>; + interrupts = ; + clock-names = + "core_clk", + "master_iface_clk", + "slave_iface_clk"; + clocks = + <&mmcc HDMI_APP_CLK>, + <&mmcc HDMI_M_AHB_CLK>, + <&mmcc HDMI_S_AHB_CLK>; + qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 + GPIO_ACTIVE_HIGH>; + qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 + GPIO_ACTIVE_HIGH>; + qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 + GPIO_ACTIVE_HIGH>; + core-vdda-supply = <&pm8921_hdmi_switch>; + hdmi-mux-supply = <&ext_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pinctrl>; + }; + + gpu: qcom,adreno-3xx@4300000 { + compatible = "qcom,adreno-3xx"; + reg = <0x04300000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core_clk", + "iface_clk", + "mem_clk", + "mem_iface_clk"; + clocks = + <&mmcc GFX3D_CLK>, + <&mmcc GFX3D_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>, + <&mmcc MMSS_IMEM_AHB_CLK>; + qcom,chipid = <0x03020002>; + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + qcom,gpu-freq = <450000000>; + }; + qcom,gpu-pwrlevel@1 { + qcom,gpu-freq = <27000000>; + }; + }; + }; + + mdp: qcom,mdp@5100000 { + compatible = "qcom,mdp"; + reg = <0x05100000 0xf0000>; + interrupts = ; + connectors = <&hdmi>; + gpus = <&gpu>; + clock-names = + "core_clk", + "iface_clk", + "lut_clk", + "src_clk", + "hdmi_clk", + "mdp_clk", + "mdp_axi_clk"; + clocks = + <&mmcc MDP_CLK>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc TV_SRC>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>, + <&mmcc MDP_AXI_CLK>; +// vdd-supply = <&footswitch_mdp>; + }; }; };