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[2001:1868:205::9]) by mx.google.com with ESMTPS id a11si28223278pdk.142.2015.04.20.06.03.08 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Apr 2015 06:03:08 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YkBK0-0003S8-3e; Mon, 20 Apr 2015 13:01:08 +0000 Received: from mail-la0-f50.google.com ([209.85.215.50]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YkBIj-0001rM-NY for linux-arm-kernel@lists.infradead.org; Mon, 20 Apr 2015 12:59:50 +0000 Received: by labbd9 with SMTP id bd9so126105094lab.2 for ; Mon, 20 Apr 2015 05:59:27 -0700 (PDT) X-Received: by 10.152.42.141 with SMTP id o13mr15715893lal.33.1429534767332; Mon, 20 Apr 2015 05:59:27 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id n10sm4295457laa.40.2015.04.20.05.59.25 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Apr 2015 05:59:26 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Mathieu Poirier Subject: [PATCH 05/13 v2] coresight: etb: let runtime PM handle core clock Date: Mon, 20 Apr 2015 14:58:58 +0200 Message-Id: <1429534746-3068-5-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1429534746-3068-1-git-send-email-linus.walleij@linaro.org> References: <1429534746-3068-1-git-send-email-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150420_055949_999311_8E24F875 X-CRM114-Status: GOOD ( 18.54 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.50 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.215.50 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Ulf Hansson , "Rafael J. Wysocki" , Russell King , Linus Walleij , Trollkarlen Marklund X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This uses runtime PM to manage the PCLK ("amba_pclk") instead of screwing around with the framework by going in and taking a copy from the amba device. The amba bus core will uprepare and disable the clock when the device is unused when CONFIG_PM is selected, else the clock will be always on. Prior to this patch, as the AMBA primecell bus code enables the PCLK, it would be left on after probe as the clk_prepare_enable() and clk_disable_unprepare() was called and thus just increase and decreas the refcount by one, without it reaching zero and actually disabling the clock. Now the runtime PM callbacks will make sure the PCLK is properly disabled after probe. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Rebased on the coresight git tree. - Added Ulf's review tag. --- drivers/hwtracing/coresight/coresight-etb10.c | 35 +++++++-------------------- 1 file changed, 9 insertions(+), 26 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 40049869aecd..f6ec3ae5a76b 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include @@ -68,7 +68,6 @@ * @dev: the device entity associated to this component. * @csdev: component vitals needed by the framework. * @miscdev: specifics to handle "/dev/xyz.etb" entry. - * @clk: the clock this component is associated to. * @spinlock: only one at a time pls. * @in_use: synchronise user space access to etb buffer. * @buf: area of memory where ETB buffer content gets sent. @@ -81,7 +80,6 @@ struct etb_drvdata { struct device *dev; struct coresight_device *csdev; struct miscdevice miscdev; - struct clk *clk; spinlock_t spinlock; atomic_t in_use; u8 *buf; @@ -92,17 +90,14 @@ struct etb_drvdata { static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) { - int ret; u32 depth = 0; - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; + pm_runtime_get_sync(drvdata->dev); /* RO registers don't need locking */ depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(drvdata->dev); return depth; } @@ -137,12 +132,9 @@ static void etb_enable_hw(struct etb_drvdata *drvdata) static int etb_enable(struct coresight_device *csdev) { struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - int ret; unsigned long flags; - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; + pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); etb_enable_hw(drvdata); @@ -252,7 +244,7 @@ static void etb_disable(struct coresight_device *csdev) drvdata->enable = false; spin_unlock_irqrestore(&drvdata->spinlock, flags); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(drvdata->dev); dev_info(drvdata->dev, "ETB disabled\n"); } @@ -339,16 +331,12 @@ static const struct file_operations etb_fops = { static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { - int ret; unsigned long flags; u32 etb_rdr, etb_sr, etb_rrp, etb_rwp; u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr; struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); - ret = clk_prepare_enable(drvdata->clk); - if (ret) - goto out; - + pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); @@ -364,7 +352,7 @@ static ssize_t status_show(struct device *dev, CS_LOCK(drvdata->base); spin_unlock_irqrestore(&drvdata->spinlock, flags); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(drvdata->dev); return sprintf(buf, "Depth:\t\t0x%x\n" @@ -377,7 +365,7 @@ static ssize_t status_show(struct device *dev, "Flush ctrl:\t0x%x\n", etb_rdr, etb_sr, etb_rrp, etb_rwp, etb_trg, etb_cr, etb_ffsr, etb_ffcr); -out: + return -EINVAL; } static DEVICE_ATTR_RO(status); @@ -449,13 +437,8 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); - drvdata->clk = adev->pclk; - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; - drvdata->buffer_depth = etb_get_buffer_depth(drvdata); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(&adev->dev); if (drvdata->buffer_depth < 0) return -EINVAL;