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[209.85.217.181]) by mx.google.com with ESMTPS id i3si7469917lbv.74.2015.04.23.22.28.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Apr 2015 22:28:59 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) client-ip=209.85.217.181; Received: by lbbzk7 with SMTP id zk7so28573350lbb.0 for ; Thu, 23 Apr 2015 22:28:59 -0700 (PDT) X-Received: by 10.112.184.70 with SMTP id es6mr5337317lbc.117.1429853339407; Thu, 23 Apr 2015 22:28:59 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.67.65 with SMTP id l1csp976699lbt; Thu, 23 Apr 2015 22:28:58 -0700 (PDT) X-Received: by 10.70.42.13 with SMTP id j13mr2991136pdl.64.1429853337671; Thu, 23 Apr 2015 22:28:57 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id gw3si15799508pac.117.2015.04.23.22.28.56; Thu, 23 Apr 2015 22:28:57 -0700 (PDT) Received-SPF: none (google.com: stable-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754487AbbDXF24 (ORCPT + 2 others); Fri, 24 Apr 2015 01:28:56 -0400 Received: from mail-ob0-f180.google.com ([209.85.214.180]:34303 "EHLO mail-ob0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754481AbbDXF2z (ORCPT ); Fri, 24 Apr 2015 01:28:55 -0400 Received: by obfe9 with SMTP id e9so30159212obf.1 for ; Thu, 23 Apr 2015 22:28:55 -0700 (PDT) X-Received: by 10.60.15.133 with SMTP id x5mr5702745oec.80.1429853335455; Thu, 23 Apr 2015 22:28:55 -0700 (PDT) Received: from localhost ([167.160.116.36]) by mx.google.com with ESMTPSA id oo10sm6015391oeb.0.2015.04.23.22.28.53 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 23 Apr 2015 22:28:54 -0700 (PDT) From: shannon.zhao@linaro.org To: stable@vger.kernel.org Cc: jslaby@suse.cz, christoffer.dall@linaro.org, shannon.zhao@linaro.org, Jonathan Austin Subject: [PATCH for 3.12.y stable 02/63] KVM: ARM: fix the size of TTBCR_{T0SZ, T1SZ} masks Date: Fri, 24 Apr 2015 13:27:00 +0800 Message-Id: <1429853281-6136-3-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1429853281-6136-1-git-send-email-shannon.zhao@linaro.org> References: <1429853281-6136-1-git-send-email-shannon.zhao@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: stable@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jonathan Austin commit 5e497046f005528464f9600a4ee04f49df713596 upstream. The T{0,1}SZ fields of TTBCR are 3 bits wide when using the long descriptor format. Likewise, the T0SZ field of the HTCR is 3-bits. KVM currently defines TTBCR_T{0,1}SZ as 3, not 7. The T0SZ mask is used to calculate the value for the HTCR, both to pick out TTBCR.T0SZ and mask off the equivalent field in the HTCR during read-modify-write. The incorrect mask size causes the (UNKNOWN) reset value of HTCR.T0SZ to leak in to the calculated HTCR value. Linux will hang when initializing KVM if HTCR's reset value has bit 2 set (sometimes the case on A7/TC2) Fixing T0SZ allows A7 cores to boot and T1SZ is also fixed for completeness. Signed-off-by: Jonathan Austin Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall Signed-off-by: Shannon Zhao --- arch/arm/include/asm/kvm_arm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h index 64e9696..d556f03 100644 --- a/arch/arm/include/asm/kvm_arm.h +++ b/arch/arm/include/asm/kvm_arm.h @@ -95,12 +95,12 @@ #define TTBCR_IRGN1 (3 << 24) #define TTBCR_EPD1 (1 << 23) #define TTBCR_A1 (1 << 22) -#define TTBCR_T1SZ (3 << 16) +#define TTBCR_T1SZ (7 << 16) #define TTBCR_SH0 (3 << 12) #define TTBCR_ORGN0 (3 << 10) #define TTBCR_IRGN0 (3 << 8) #define TTBCR_EPD0 (1 << 7) -#define TTBCR_T0SZ 3 +#define TTBCR_T0SZ (7 << 0) #define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0) /* Hyp System Trap Register */