| Message ID | 20210713144621.605140-3-dinguyen@kernel.org |
|---|---|
| State | Accepted |
| Commit | d17929eb1066d1c1653aae9bb4396a9f1d6602ac |
| Headers | show |
| Series | [1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk | expand |
Quoting Dinh Nguyen (2021-07-13 07:46:21) > Add the bypass register for the s2f_user0_clk. > > Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") > Cc: stable@vger.kernel.org > Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- Applied to clk-next
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 7baaa16dea7b..242e94c0cf8a 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -280,7 +280,7 @@ static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = { { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux, ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0}, { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux, - ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0}, + ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, 2}, { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux, ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5}, { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
Add the bypass register for the s2f_user0_clk. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- drivers/clk/socfpga/clk-agilex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)