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[RFC,4/5] arm64: Unmask PMU bits in debug feature register

Message ID 1430417667-4245-4-git-send-email-christopher.covington@linaro.org
State New
Headers show

Commit Message

Christopher Covington April 30, 2015, 6:14 p.m. UTC 
The previously missing registers are now present in QEMU.

Signed-off-by: Christopher Covington <christopher.covington@linaro.org>
---
 target-arm/helper.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)
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Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 863cfd0..3e6fb0b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3149,12 +3149,7 @@  void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_CONST,
-              /* We mask out the PMUVer field, because we don't currently
-               * implement the PMU. Not advertising it prevents the guest
-               * from trying to use it and getting UNDEFs on registers we
-               * don't implement.
-               */
-              .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
+              .resetvalue = cpu->id_aa64dfr0 },
             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
               .access = PL1_R, .type = ARM_CP_CONST,