[ARM,AArch64,testsuite] AdvSIMD intrinsics tests cleanup: remove useless expected values.

Message ID	CAKdteOYzjuAJ1ajWCwO=0vv2okow-UipDiBoNRaE2Hc6Wvy8MA@mail.gmail.com
State	Accepted
Commit	90c19438a26683180babe6fd8007b5567cf914d3
Headers	show Return-Path: <patchwork-forward+bncBDNJJ5OM3EFRBWEJRKVAKGQEYNGLUUQ@linaro.org> Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::231 as permitted sender) client-ip=2a00:1450:4010:c03::231; Received-SPF: pass (google.com: domain of gcc-patches-return-396551-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list Sender: gcc-patches-owner@gcc.gnu.org MIME-Version: 1.0 Date: Thu, 30 Apr 2015 21:38:04 +0200 Message-ID: <CAKdteOYzjuAJ1ajWCwO=0vv2okow-UipDiBoNRaE2Hc6Wvy8MA@mail.gmail.com> Subject: [ARM, AArch64][testsuite] AdvSIMD intrinsics tests cleanup: remove useless expected values. From: Christophe Lyon <christophe.lyon@linaro.org> To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org> Content-Type: multipart/mixed; boundary=001a11473b240002ea0514f63c8d

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op.inc index 3483e0e..54652a2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op.inc @@ -55,7 +55,22 @@ void FNNAME (INSN_NAME) (void) /* Apply a binary operator named INSN_NAME. */ TEST_MACRO_ALL_VARIANTS_1_5(TEST_BINARY_OP, INSN_NAME); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); #ifdef EXTRA_TESTS EXTRA_TESTS(); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc index c09a468..c91709f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc @@ -76,7 +76,22 @@ void FNNAME (INSN_NAME) (void) TEST_BINARY_SAT_OP(INSN_NAME, q, uint, u, 32, 4, expected_cumulative_sat, ""); TEST_BINARY_SAT_OP(INSN_NAME, q, uint, u, 64, 2, expected_cumulative_sat, ""); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); #ifdef EXTRA_TESTS EXTRA_TESTS(); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_op.inc index 33f9b5f..8b117f7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_op.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_op.inc @@ -57,7 +57,12 @@ void FNNAME (INSN_NAME) (void) TEST_UNARY_OP(INSN_NAME, q, int, s, 16, 8); TEST_UNARY_OP(INSN_NAME, q, int, s, 32, 4); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); #ifdef EXTRA_TESTS EXTRA_TESTS(); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc index bd4c8fb..7cfb01c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc @@ -60,7 +60,12 @@ void FNNAME (INSN_NAME) (void) TEST_VADDL(INSN_NAME, uint, u, 16, 32, 4); TEST_VADDL(INSN_NAME, uint, u, 32, 64, 2); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc index c535557..876b7c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc @@ -60,7 +60,12 @@ void FNNAME (INSN_NAME) (void) TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4); TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaba.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaba.c index 2465cd2..e3692f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaba.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaba.c @@ -7,16 +7,10 @@ VECT_VAR_DECL(expected,int,8,8) [] = { 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd }; VECT_VAR_DECL(expected,int,16,4) [] = { 0x16, 0x17, 0x18, 0x19 }; VECT_VAR_DECL(expected,int,32,2) [] = { 0x20, 0x21 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0x907, 0x908, 0x909, 0x90a }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe7, 0xffffffe8 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x5e, 0x5f, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, @@ -24,8 +18,6 @@ VECT_VAR_DECL(expected,int,8,16) [] = { 0x5e, 0x5f, 0x60, 0x61, VECT_VAR_DECL(expected,int,16,8) [] = { 0xb9c, 0xb9d, 0xb9e, 0xb9f, 0xba0, 0xba1, 0xba2, 0xba3 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x26e0, 0x26e1, 0x26e2, 0x26e3 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, 0x0, 0x1, 0x2, 0x3, @@ -33,16 +25,6 @@ VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf8, 0xf9, 0xfa, 0xfb, VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xfffe, 0xffff, 0x0 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xc, 0xd, 0xe, 0xf }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #define TEST_MSG "VABA/VABAQ" void exec_vaba (void) @@ -132,7 +114,18 @@ void exec_vaba (void) TEST_VABA(q, uint, u, 16, 8); TEST_VABA(q, uint, u, 32, 4); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabal.c index cd31062..1122a6b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabal.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabal.c @@ -3,45 +3,15 @@ #include "compute-ref-data.h" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff6, 0xfff7, 0xfff8, 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x16, 0x17, 0x18, 0x19 }; VECT_VAR_DECL(expected,int,64,2) [] = { 0x20, 0x21 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,uint,16,8) [] = { 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x907, 0x908, 0x909, 0x90a }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffe7, 0xffffffe8 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results for cases with input values chosen to test possible intermediate overflow. */ @@ -121,7 +91,12 @@ void exec_vabal (void) TEST_VABAL(uint, u, 16, 32, 4); TEST_VABAL(uint, u, 32, 64, 2); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); /* Use values that could lead to overflow intermediate * calculations. */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c index e95404f..67d2af1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c @@ -8,15 +8,10 @@ VECT_VAR_DECL(expected,int,8,8) [] = { 0x11, 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa }; VECT_VAR_DECL(expected,int,16,4) [] = { 0x3, 0x2, 0x1, 0x0 }; VECT_VAR_DECL(expected,int,32,2) [] = { 0x18, 0x17 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0xef, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe3, 0xffe4, 0xffe5, 0xffe6 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe8, 0xffffffe9 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x41c26666, 0x41ba6666 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, @@ -25,8 +20,6 @@ VECT_VAR_DECL(expected,int,8,16) [] = { 0x1a, 0x19, 0x18, 0x17, VECT_VAR_DECL(expected,int,16,8) [] = { 0x4, 0x3, 0x2, 0x1, 0x0, 0x1, 0x2, 0x3 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x30, 0x2f, 0x2e, 0x2d }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,16) [] = { 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xf0, 0xf1, @@ -35,14 +28,6 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xffe4, 0xffe5, 0xffe6, 0xffe7, 0xffe8, 0xffe9, 0xffea, 0xffeb }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffd0, 0xffffffd1, 0xffffffd2, 0xffffffd3 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x42407ae1, 0x423c7ae1, 0x42387ae1, 0x42347ae1 }; @@ -130,7 +115,20 @@ void exec_vabd (void) TEST_VABD(q, uint, u, 32, 4); TEST_VABD(q, float, f, 32, 4); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); /* Extra FP tests with special values (-0.0, ....) */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdl.c index 28018ab..7f7cc67 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdl.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdl.c @@ -3,45 +3,15 @@ #include "compute-ref-data.h" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0x11, 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x3, 0x2, 0x1, 0x0 }; VECT_VAR_DECL(expected,int,64,2) [] = { 0x18, 0x17 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,uint,16,8) [] = { 0xef, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffe3, 0xffe4, 0xffe5, 0xffe6 }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffe8, 0xffffffe9 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #define TEST_MSG "VABDL" void exec_vabdl (void) @@ -99,7 +69,12 @@ void exec_vabdl (void) TEST_VABDL(uint, u, 16, 32, 4); TEST_VABDL(uint, u, 32, 64, 2); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c index ca3901a..9c80ef1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c @@ -12,41 +12,11 @@ VECT_VAR_DECL(expected,int,8,8) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9 }; VECT_VAR_DECL(expected,int,16,4) [] = { 0x10, 0xf, 0xe, 0xd }; VECT_VAR_DECL(expected,int,32,2) [] = { 0x10, 0xf }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results for float32 variants. Needs to be separated since the generic test function does not test floating-point diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c index f08c620..7be1401 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c @@ -18,10 +18,6 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0x4, 0x5, 0x6, 0x7, VECT_VAR_DECL(expected,uint,16,4) [] = { 0xe, 0xf, 0x10, 0x11 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0x18, 0x19 }; VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff2 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xf0, 0xf1, @@ -40,14 +36,6 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff3, 0xfff4, 0xfff5, 0xfff6, VECT_VAR_DECL(expected,uint,32,4) [] = { 0x27, 0x28, 0x29, 0x2a }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff3, 0xfffffffffffffff4 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results for float32 variants. Needs to be separated since the generic test function does not test floating-point diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c index 020d9f8..fd8a64f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c @@ -6,46 +6,16 @@ #define TEST_MSG "VADDL" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0xffe3, 0xffe4, 0xffe5, 0xffe6, 0xffe7, 0xffe8, 0xffe9, 0xffea }; VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffe2, 0xffffffe3, 0xffffffe4, 0xffffffe5 }; VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffe0, 0xffffffffffffffe1 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,uint,16,8) [] = { 0x1e3, 0x1e4, 0x1e5, 0x1e6, 0x1e7, 0x1e8, 0x1e9, 0x1ea }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x1ffe1, 0x1ffe2, 0x1ffe3, 0x1ffe4 }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0x1ffffffe0, 0x1ffffffe1 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #include "vXXXl.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c index 27f54f6..bfd9ef7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c @@ -6,46 +6,16 @@ #define TEST_MSG "VADDW" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0xffe3, 0xffe4, 0xffe5, 0xffe6, 0xffe7, 0xffe8, 0xffe9, 0xffea }; VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffe2, 0xffffffe3, 0xffffffe4, 0xffffffe5 }; VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffe0, 0xffffffffffffffe1 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,uint,16,8) [] = { 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffe1, 0xffe2, 0xffe3, 0xffe4 }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffe0, 0xffffffe1 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #include "vXXXw.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vand.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vand.c index e7e65dd..3ce13a3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vand.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vand.c @@ -14,10 +14,6 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0x10, 0x10, 0x10, 0x10, VECT_VAR_DECL(expected,uint,16,4) [] = { 0x10, 0x10, 0x12, 0x12 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0x20, 0x20 }; VECT_VAR_DECL(expected,uint,64,1) [] = { 0x0 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf0, 0xf2, 0xf2, 0xf4, 0xf4, 0xf6, 0xf6, 0xf0, 0xf0, 0xf2, 0xf2, @@ -35,11 +31,3 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0x0, 0x1, 0x2, 0x3, 0x0, 0x1, 0x2, 0x3 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x30, 0x31, 0x32, 0x33 }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0x0, 0x1 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbic.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbic.c index 83e57ff..5a3989f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbic.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbic.c @@ -14,10 +14,6 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe0, 0xe1, 0xe2, 0xe3, VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe0, 0xffe1, 0xffe0, 0xffe1 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffd0, 0xffffffd1 }; VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x8, 0x9, 0x8, 0x9, @@ -36,11 +32,3 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffc0, 0xffffffc0, 0xffffffc0, 0xffffffc0 }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0, 0xfffffffffffffff0 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c index 219d03f..1fadf66 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c @@ -4,48 +4,9 @@ #include "cmp_fp_op.inc" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0x0 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0xffffffff, 0x0 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff, diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c index ed62c85..b1144a2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c @@ -4,47 +4,9 @@ #include "cmp_fp_op.inc" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0x0 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff, diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c index cc83a39..bff9e4a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c @@ -4,46 +4,8 @@ #include "cmp_fp_op.inc" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c index a60536e..ed652eb 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c @@ -4,46 +4,8 @@ #include "cmp_fp_op.inc" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0xffffffff }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c index aa095df..1e21d50 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c @@ -8,29 +8,9 @@ void exec_vceq_p8(void); #include "cmp_op.inc" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x0 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0x0, 0x0, 0xffff, 0x0 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0x0 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -38,16 +18,6 @@ VECT_VAR_DECL(expected,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0, VECT_VAR_DECL(expected,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffff, 0x0 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0x0 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected_uint,uint,8,8) [] = { 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c index 236fd82..22a5d67 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c @@ -4,29 +4,9 @@ #include "cmp_op.inc" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0x0, 0x0, 0xffff, 0xffff }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -34,16 +14,6 @@ VECT_VAR_DECL(expected,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0, VECT_VAR_DECL(expected,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffff, 0xffff }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected_uint,uint,8,8) [] = { 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c index 23aaa01..c44819a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c @@ -4,29 +4,9 @@ #include "cmp_op.inc" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0x0, 0x0, 0x0, 0xffff }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0xffffffff }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -34,16 +14,6 @@ VECT_VAR_DECL(expected,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0, VECT_VAR_DECL(expected,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffff }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected_uint,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c index e4cad0c..a59b543 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c @@ -4,30 +4,10 @@ #include "cmp_op.inc" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffff, 0xffff, 0xffff, 0x0 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0x0 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,16) [] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -36,16 +16,6 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0xffffffff, 0x0 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected_uint,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcls.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcls.c index 1d56c12..5f7565d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcls.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcls.c @@ -6,16 +6,6 @@ VECT_VAR_DECL(expected,int,8,8) [] = { 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6 }; VECT_VAR_DECL(expected,int,16,4) [] = { 0x2, 0x2, 0x2, 0x2 }; VECT_VAR_DECL(expected,int,32,2) [] = { 0x19, 0x19 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, @@ -23,45 +13,12 @@ VECT_VAR_DECL(expected,int,8,16) [] = { 0x7, 0x7, 0x7, 0x7, VECT_VAR_DECL(expected,int,16,8) [] = { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x14, 0x14, 0x14, 0x14 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results with negative input. */ VECT_VAR_DECL(expected_with_negative,int,8,8) [] = { 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7 }; VECT_VAR_DECL(expected_with_negative,int,16,4) [] = { 0x1, 0x1, 0x1, 0x1 }; VECT_VAR_DECL(expected_with_negative,int,32,2) [] = { 0x1, 0x1 }; -VECT_VAR_DECL(expected_with_negative,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected_with_negative,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_with_negative,uint,16,4) [] = { 0x3333, 0x3333, - 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_with_negative,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_with_negative,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected_with_negative,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_with_negative,poly,16,4) [] = { 0x3333, 0x3333, - 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_with_negative,hfloat,32,2) [] = { 0x33333333, - 0x33333333 }; VECT_VAR_DECL(expected_with_negative,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -69,32 +26,6 @@ VECT_VAR_DECL(expected_with_negative,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, VECT_VAR_DECL(expected_with_negative,int,16,8) [] = { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }; VECT_VAR_DECL(expected_with_negative,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; -VECT_VAR_DECL(expected_with_negative,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_with_negative,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_with_negative,uint,16,8) [] = { 0x3333, 0x3333, - 0x3333, 0x3333, - 0x3333, 0x3333, - 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_with_negative,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_with_negative,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_with_negative,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_with_negative,poly,16,8) [] = { 0x3333, 0x3333, - 0x3333, 0x3333, - 0x3333, 0x3333, - 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_with_negative,hfloat,32,4) [] = { 0x33333333, - 0x33333333, - 0x33333333, - 0x33333333 }; #define INSN_NAME vcls #define TEST_MSG "VCLS/VCLSQ" @@ -146,7 +77,13 @@ FNNAME (INSN_NAME) TEST_UNARY_OP(INSN_NAME, q, int, s, 16, 8); TEST_UNARY_OP(INSN_NAME, q, int, s, 32, 4); - CHECK_RESULTS (TEST_MSG, " (positive input)"); +#define MSG_POSITIVE " (positive input)" + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, MSG_POSITIVE); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, MSG_POSITIVE); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, MSG_POSITIVE); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, MSG_POSITIVE); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, MSG_POSITIVE); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, MSG_POSITIVE); /* Fill input vector with arbitrary values (negative). */ VDUP(vector, , int, s, 8, 8, 0xFF); @@ -164,7 +101,13 @@ FNNAME (INSN_NAME) TEST_UNARY_OP(INSN_NAME, q, int, s, 16, 8); TEST_UNARY_OP(INSN_NAME, q, int, s, 32, 4); - CHECK_RESULTS_NAMED (TEST_MSG, expected_with_negative, " (negative input)"); +#define MSG_NEGATIVE " (negative input)" + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_with_negative, MSG_NEGATIVE); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_with_negative, MSG_NEGATIVE); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_with_negative, MSG_NEGATIVE); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_with_negative, MSG_NEGATIVE); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_with_negative, MSG_NEGATIVE); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_with_negative, MSG_NEGATIVE); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c index d437eae..6ef2b4c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c @@ -4,30 +4,10 @@ #include "cmp_op.inc" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffff, 0xffff, 0x0, 0x0 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0x0 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, - 0x333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,16) [] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -35,16 +15,6 @@ VECT_VAR_DECL(expected,uint,8,16) [] = { 0xff, 0xff, 0xff, 0xff, VECT_VAR_DECL(expected,uint,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0, 0x0 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected_uint,uint,8,8) [] = { 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclz.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclz.c index ad28d2d..5d5e932 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclz.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclz.c @@ -6,36 +6,18 @@ VECT_VAR_DECL(expected,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; VECT_VAR_DECL(expected,int,16,4) [] = { 0x3, 0x3, 0x3, 0x3 }; VECT_VAR_DECL(expected,int,32,2) [] = { 0x11, 0x11 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0x5, 0x5 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x3, 0x3, 0x3, 0x3 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,16) [] = { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }; VECT_VAR_DECL(expected,uint,16,8) [] = { 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0x1f, 0x1f, 0x1f, 0x1f }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results with input=0. */ @@ -43,16 +25,10 @@ VECT_VAR_DECL(expected_with_0,int,8,8) [] = { 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8 }; VECT_VAR_DECL(expected_with_0,int,16,4) [] = { 0x10, 0x10, 0x10, 0x10 }; VECT_VAR_DECL(expected_with_0,int,32,2) [] = { 0x20, 0x20 }; -VECT_VAR_DECL(expected_with_0,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_with_0,uint,8,8) [] = { 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8 }; VECT_VAR_DECL(expected_with_0,uint,16,4) [] = { 0x10, 0x10, 0x10, 0x10 }; VECT_VAR_DECL(expected_with_0,uint,32,2) [] = { 0x20, 0x20 }; -VECT_VAR_DECL(expected_with_0,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected_with_0,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_with_0,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_with_0,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected_with_0,int,8,16) [] = { 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, @@ -60,8 +36,6 @@ VECT_VAR_DECL(expected_with_0,int,8,16) [] = { 0x8, 0x8, 0x8, 0x8, VECT_VAR_DECL(expected_with_0,int,16,8) [] = { 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10 }; VECT_VAR_DECL(expected_with_0,int,32,4) [] = { 0x20, 0x20, 0x20, 0x20 }; -VECT_VAR_DECL(expected_with_0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_with_0,uint,8,16) [] = { 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, @@ -69,16 +43,6 @@ VECT_VAR_DECL(expected_with_0,uint,8,16) [] = { 0x8, 0x8, 0x8, 0x8, VECT_VAR_DECL(expected_with_0,uint,16,8) [] = { 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10 }; VECT_VAR_DECL(expected_with_0,uint,32,4) [] = { 0x20, 0x20, 0x20, 0x20 }; -VECT_VAR_DECL(expected_with_0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_with_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_with_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_with_0,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #define INSN_NAME vclz #define TEST_MSG "VCLZ/VCLZQ" @@ -154,7 +118,18 @@ FNNAME (INSN_NAME) TEST_UNARY_OP(INSN_NAME, q, uint, u, 16, 8); TEST_UNARY_OP(INSN_NAME, q, uint, u, 32, 4); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); /* Test with zero as input. */ VDUP(vector, , int, s, 8, 8, 0); @@ -184,7 +159,19 @@ FNNAME (INSN_NAME) TEST_UNARY_OP(INSN_NAME, q, uint, u, 16, 8); TEST_UNARY_OP(INSN_NAME, q, uint, u, 32, 4); - CHECK_RESULTS_NAMED (TEST_MSG, expected_with_0, " (input=0)"); +#define MSG_ZERO " (input=0)" + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_with_0, MSG_ZERO); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_with_0, MSG_ZERO); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcnt.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcnt.c index 4d9f0ce..ddc0865 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcnt.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcnt.c @@ -4,37 +4,14 @@ /* Expected results. */ VECT_VAR_DECL(expected,int,8,8) [] = { 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,16) [] = { 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,poly,8,16) [] = { 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #define INSN_NAME vcnt #define TEST_MSG "VCNT/VCNTQ" @@ -86,7 +63,12 @@ FNNAME (INSN_NAME) TEST_UNARY_OP(INSN_NAME, q, uint, u, 8, 16); TEST_UNARY_OP(INSN_NAME, q, poly, p, 8, 16); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c index 6d5a854..295768a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c @@ -3,20 +3,6 @@ #include "compute-ref-data.h" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0x11, 0x11, 0x11, 0x11, @@ -88,7 +74,17 @@ void exec_vcombine (void) TEST_VCOMBINE(poly, p, 16, 4, 8); TEST_VCOMBINE(float, f, 32, 2, 4); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c index 686358d..b2289d3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c @@ -17,34 +17,6 @@ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12 }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xdef0, 0x9abc, 0x5678, 0x1234 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x9abcdef0, 0x12345678 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #define INSN_NAME vcreate #define TEST_MSG "VCREATE" @@ -113,7 +85,17 @@ FNNAME (INSN_NAME) TEST_VCREATE(poly, p, 8, 8); TEST_VCREATE(poly, p, 16, 4); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/veor.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/veor.c index 474b225..5e30c25 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/veor.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/veor.c @@ -14,10 +14,6 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe4, 0xe5, 0xe6, 0xe7, VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffee, 0xffef, 0xffec, 0xffed }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffd8, 0xffffffd9 }; VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff2 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x6, 0x7, 0x4, 0x5, 0x2, 0x3, 0x0, 0x1, 0xe, 0xf, 0xc, 0xd, @@ -37,11 +33,3 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffc7, 0xffffffc6, 0xffffffc5, 0xffffffc4 }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff3, 0xfffffffffffffff2 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c index 69ad90b..d758112 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c @@ -17,34 +17,6 @@ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #define TEST_MSG "VGET_HIGH" void exec_vget_high (void) @@ -76,7 +48,17 @@ void exec_vget_high (void) TEST_VGET_HIGH(poly, p, 16, 4, 8); TEST_VGET_HIGH(float, f, 32, 2, 4); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c index db4a001..12ecfc2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c @@ -17,34 +17,6 @@ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #define TEST_MSG "VGET_LOW" void exec_vget_low (void) @@ -76,7 +48,17 @@ void exec_vget_low (void) TEST_VGET_LOW(poly, p, 16, 4, 8); TEST_VGET_LOW(float, f, 32, 2, 4); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c index fe00640..f20aa03 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c @@ -27,8 +27,6 @@ VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; VECT_VAR_DECL(expected_vld2_0,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected_vld2_0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld2_0,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, @@ -37,8 +35,6 @@ VECT_VAR_DECL(expected_vld2_0,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected_vld2_0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, @@ -71,8 +67,6 @@ VECT_VAR_DECL(expected_vld2_1,int,16,8) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xfffe, 0xffff }; VECT_VAR_DECL(expected_vld2_1,int,32,4) [] = { 0xfffffff4, 0xfffffff5, 0xfffffff6, 0xfffffff7 }; -VECT_VAR_DECL(expected_vld2_1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld2_1,uint,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, @@ -81,8 +75,6 @@ VECT_VAR_DECL(expected_vld2_1,uint,16,8) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xfffe, 0xffff }; VECT_VAR_DECL(expected_vld2_1,uint,32,4) [] = { 0xfffffff4, 0xfffffff5, 0xfffffff6, 0xfffffff7 }; -VECT_VAR_DECL(expected_vld2_1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld2_1,poly,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, @@ -115,8 +107,6 @@ VECT_VAR_DECL(expected_vld3_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; VECT_VAR_DECL(expected_vld3_0,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected_vld3_0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_0,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, @@ -125,8 +115,6 @@ VECT_VAR_DECL(expected_vld3_0,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; VECT_VAR_DECL(expected_vld3_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected_vld3_0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_0,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, @@ -159,8 +147,6 @@ VECT_VAR_DECL(expected_vld3_1,int,16,8) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xfffe, 0xffff }; VECT_VAR_DECL(expected_vld3_1,int,32,4) [] = { 0xfffffff4, 0xfffffff5, 0xfffffff6, 0xfffffff7 }; -VECT_VAR_DECL(expected_vld3_1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_1,uint,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, @@ -169,8 +155,6 @@ VECT_VAR_DECL(expected_vld3_1,uint,16,8) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xfffe, 0xffff }; VECT_VAR_DECL(expected_vld3_1,uint,32,4) [] = { 0xfffffff4, 0xfffffff5, 0xfffffff6, 0xfffffff7 }; -VECT_VAR_DECL(expected_vld3_1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_1,poly,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, @@ -206,8 +190,6 @@ VECT_VAR_DECL(expected_vld3_2,int,16,8) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 }; VECT_VAR_DECL(expected_vld3_2,int,32,4) [] = { 0xfffffff8, 0xfffffff9, 0xfffffffa, 0xfffffffb }; -VECT_VAR_DECL(expected_vld3_2,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_2,uint,8,16) [] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, @@ -216,8 +198,6 @@ VECT_VAR_DECL(expected_vld3_2,uint,16,8) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 }; VECT_VAR_DECL(expected_vld3_2,uint,32,4) [] = { 0xfffffff8, 0xfffffff9, 0xfffffffa, 0xfffffffb }; -VECT_VAR_DECL(expected_vld3_2,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_2,poly,8,16) [] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, @@ -252,8 +232,6 @@ VECT_VAR_DECL(expected_vld4_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; VECT_VAR_DECL(expected_vld4_0,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected_vld4_0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_0,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, @@ -262,8 +240,6 @@ VECT_VAR_DECL(expected_vld4_0,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; VECT_VAR_DECL(expected_vld4_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected_vld4_0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_0,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, @@ -296,8 +272,6 @@ VECT_VAR_DECL(expected_vld4_1,int,16,8) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xfffe, 0xffff }; VECT_VAR_DECL(expected_vld4_1,int,32,4) [] = { 0xfffffff4, 0xfffffff5, 0xfffffff6, 0xfffffff7 }; -VECT_VAR_DECL(expected_vld4_1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_1,uint,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, @@ -306,8 +280,6 @@ VECT_VAR_DECL(expected_vld4_1,uint,16,8) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xfffe, 0xffff }; VECT_VAR_DECL(expected_vld4_1,uint,32,4) [] = { 0xfffffff4, 0xfffffff5, 0xfffffff6, 0xfffffff7 }; -VECT_VAR_DECL(expected_vld4_1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_1,poly,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, @@ -340,8 +312,6 @@ VECT_VAR_DECL(expected_vld4_2,int,16,8) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 }; VECT_VAR_DECL(expected_vld4_2,int,32,4) [] = { 0xfffffff8, 0xfffffff9, 0xfffffffa, 0xfffffffb }; -VECT_VAR_DECL(expected_vld4_2,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_2,uint,8,16) [] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, @@ -350,8 +320,6 @@ VECT_VAR_DECL(expected_vld4_2,uint,16,8) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 }; VECT_VAR_DECL(expected_vld4_2,uint,32,4) [] = { 0xfffffff8, 0xfffffff9, 0xfffffffa, 0xfffffffb }; -VECT_VAR_DECL(expected_vld4_2,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_2,poly,8,16) [] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, @@ -384,8 +352,6 @@ VECT_VAR_DECL(expected_vld4_3,int,16,8) [] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf }; VECT_VAR_DECL(expected_vld4_3,int,32,4) [] = { 0xfffffffc, 0xfffffffd, 0xfffffffe, 0xffffffff }; -VECT_VAR_DECL(expected_vld4_3,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_3,uint,8,16) [] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, @@ -394,8 +360,6 @@ VECT_VAR_DECL(expected_vld4_3,uint,16,8) [] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf }; VECT_VAR_DECL(expected_vld4_3,uint,32,4) [] = { 0xfffffffc, 0xfffffffd, 0xfffffffe, 0xffffffff }; -VECT_VAR_DECL(expected_vld4_3,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_3,poly,8,16) [] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, @@ -500,6 +464,32 @@ void exec_vldX (void) TEST_EXTRA_CHUNK(poly, 16, 8, X, Y); \ TEST_EXTRA_CHUNK(float, 32, 4, X, Y) + /* vldX supports all vector types except [u]int64x2. */ +#define CHECK_RESULTS_VLDX(test_name,EXPECTED,comment) \ + { \ + CHECK(test_name, int, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, int, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK(test_name, int, 32, 2, PRIx32, EXPECTED, comment); \ + CHECK(test_name, int, 64, 1, PRIx64, EXPECTED, comment); \ + CHECK(test_name, uint, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment); \ + CHECK(test_name, uint, 64, 1, PRIx64, EXPECTED, comment); \ + CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment); \ + \ + CHECK(test_name, int, 8, 16, PRIx8, EXPECTED, comment); \ + CHECK(test_name, int, 16, 8, PRIx16, EXPECTED, comment); \ + CHECK(test_name, int, 32, 4, PRIx32, EXPECTED, comment); \ + CHECK(test_name, uint, 8, 16, PRIx8, EXPECTED, comment); \ + CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment); \ + CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment); \ + CHECK(test_name, poly, 8, 16, PRIx8, EXPECTED, comment); \ + CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment); \ + CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment); \ + } \ + DECL_ALL_VLDX(2); DECL_ALL_VLDX(3); DECL_ALL_VLDX(4); @@ -650,39 +640,39 @@ void exec_vldX (void) clean_results (); #define TEST_MSG "VLD2/VLD2Q" TEST_ALL_VLDX(2); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_0, "chunk 0"); + CHECK_RESULTS_VLDX (TEST_MSG, expected_vld2_0, "chunk 0"); TEST_ALL_EXTRA_CHUNKS(2, 1); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_1, "chunk 1"); + CHECK_RESULTS_VLDX (TEST_MSG, expected_vld2_1, "chunk 1"); /* Check vld3/vld3q. */ clean_results (); #undef TEST_MSG #define TEST_MSG "VLD3/VLD3Q" TEST_ALL_VLDX(3); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_0, "chunk 0"); + CHECK_RESULTS_VLDX (TEST_MSG, expected_vld3_0, "chunk 0"); TEST_ALL_EXTRA_CHUNKS(3, 1); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_1, "chunk 1"); + CHECK_RESULTS_VLDX (TEST_MSG, expected_vld3_1, "chunk 1"); TEST_ALL_EXTRA_CHUNKS(3, 2); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_2, "chunk 2"); + CHECK_RESULTS_VLDX (TEST_MSG, expected_vld3_2, "chunk 2"); /* Check vld4/vld4q. */ clean_results (); #undef TEST_MSG #define TEST_MSG "VLD4/VLD4Q" TEST_ALL_VLDX(4); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_0, "chunk 0"); + CHECK_RESULTS_VLDX (TEST_MSG, expected_vld4_0, "chunk 0"); TEST_ALL_EXTRA_CHUNKS(4, 1); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_1, "chunk 1"); + CHECK_RESULTS_VLDX (TEST_MSG, expected_vld4_1, "chunk 1"); TEST_ALL_EXTRA_CHUNKS(4, 2); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_2, "chunk 2"); + CHECK_RESULTS_VLDX (TEST_MSG, expected_vld4_2, "chunk 2"); TEST_ALL_EXTRA_CHUNKS(4, 3); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_3, "chunk 3"); + CHECK_RESULTS_VLDX (TEST_MSG, expected_vld4_3, "chunk 3"); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c index 53cd8f3..c66dade 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c @@ -19,34 +19,6 @@ VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1, 0xf0, 0xf1, 0xf0, 0xf1 }; VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 }; VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; -VECT_VAR_DECL(expected_vld2_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld2_0,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld2_0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld2_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld2_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld2_0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* vld2_dup/chunk 1. */ VECT_VAR_DECL(expected_vld2_1,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1, @@ -64,34 +36,6 @@ VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1, VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 }; VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; -VECT_VAR_DECL(expected_vld2_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld2_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld2_1,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld2_1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld2_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld2_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld2_1,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld2_1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld2_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld2_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld2_1,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* vld3_dup/chunk 0. */ VECT_VAR_DECL(expected_vld3_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0, @@ -111,34 +55,6 @@ VECT_VAR_DECL(expected_vld3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0, VECT_VAR_DECL(expected_vld3_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff0 }; VECT_VAR_DECL(expected_vld3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; -VECT_VAR_DECL(expected_vld3_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld3_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld3_0,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld3_0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld3_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld3_0,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld3_0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld3_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld3_0,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* vld3_dup/chunk 1. */ VECT_VAR_DECL(expected_vld3_1,int,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2, @@ -158,34 +74,6 @@ VECT_VAR_DECL(expected_vld3_1,poly,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2, VECT_VAR_DECL(expected_vld3_1,poly,16,4) [] = { 0xfff1, 0xfff2, 0xfff0, 0xfff1 }; VECT_VAR_DECL(expected_vld3_1,hfloat,32,2) [] = { 0xc1600000, 0xc1800000 }; -VECT_VAR_DECL(expected_vld3_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld3_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld3_1,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld3_1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld3_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld3_1,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld3_1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld3_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld3_1,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* vld3_dup/chunk 2. */ VECT_VAR_DECL(expected_vld3_2,int,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1, @@ -205,34 +93,6 @@ VECT_VAR_DECL(expected_vld3_2,poly,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1, VECT_VAR_DECL(expected_vld3_2,poly,16,4) [] = { 0xfff2, 0xfff0, 0xfff1, 0xfff2 }; VECT_VAR_DECL(expected_vld3_2,hfloat,32,2) [] = { 0xc1700000, 0xc1600000 }; -VECT_VAR_DECL(expected_vld3_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld3_2,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld3_2,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld3_2,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld3_2,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld3_2,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld3_2,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld3_2,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld3_2,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* vld4_dup/chunk 0. */ VECT_VAR_DECL(expected_vld4_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, @@ -250,34 +110,6 @@ VECT_VAR_DECL(expected_vld4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf0, 0xf1, 0xf2, 0xf3 }; VECT_VAR_DECL(expected_vld4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected_vld4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; -VECT_VAR_DECL(expected_vld4_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_0,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld4_0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_0,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld4_0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_0,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* vld4_dup/chunk 1. */ VECT_VAR_DECL(expected_vld4_1,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, @@ -294,34 +126,6 @@ VECT_VAR_DECL(expected_vld4_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf0, 0xf1, 0xf2, 0xf3 }; VECT_VAR_DECL(expected_vld4_1,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected_vld4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; -VECT_VAR_DECL(expected_vld4_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_1,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld4_1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_1,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld4_1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_1,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* vld4_dup/chunk 2. */ VECT_VAR_DECL(expected_vld4_2,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, @@ -338,34 +142,6 @@ VECT_VAR_DECL(expected_vld4_2,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf0, 0xf1, 0xf2, 0xf3 }; VECT_VAR_DECL(expected_vld4_2,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected_vld4_2,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; -VECT_VAR_DECL(expected_vld4_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_2,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_2,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld4_2,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_2,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_2,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld4_2,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_2,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_2,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* vld4_dup/chunk3. */ VECT_VAR_DECL(expected_vld4_3,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, @@ -382,33 +158,6 @@ VECT_VAR_DECL(expected_vld4_3,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf0, 0xf1, 0xf2, 0xf3 }; VECT_VAR_DECL(expected_vld4_3,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected_vld4_3,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; -VECT_VAR_DECL(expected_vld4_3,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_3,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_3,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld4_3,int,64,2) [] = { 0x3333333333333333, 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_3,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_3,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_3,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected_vld4_3,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_3,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_vld4_3,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_vld4_3,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; void exec_vldX_dup (void) { @@ -478,6 +227,21 @@ void exec_vldX_dup (void) TEST_EXTRA_CHUNK(poly, 16, 4, X, Y); \ TEST_EXTRA_CHUNK(float, 32, 2, X, Y) + /* vldX_dup supports only 64-bit inputs. */ +#define CHECK_RESULTS_VLDX_DUP(test_name,EXPECTED,comment) \ + { \ + CHECK(test_name, int, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, int, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK(test_name, int, 32, 2, PRIx32, EXPECTED, comment); \ + CHECK(test_name, int, 64, 1, PRIx64, EXPECTED, comment); \ + CHECK(test_name, uint, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment); \ + CHECK(test_name, uint, 64, 1, PRIx64, EXPECTED, comment); \ + CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment); \ + } \ DECL_ALL_VLDX_DUP(2); DECL_ALL_VLDX_DUP(3); @@ -629,39 +393,39 @@ void exec_vldX_dup (void) clean_results (); #define TEST_MSG "VLD2_DUP/VLD2Q_DUP" TEST_ALL_VLDX_DUP(2); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_0, "chunk 0"); + CHECK_RESULTS_VLDX_DUP (TEST_MSG, expected_vld2_0, "chunk 0"); TEST_ALL_EXTRA_CHUNKS(2, 1); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_1, "chunk 1"); + CHECK_RESULTS_VLDX_DUP (TEST_MSG, expected_vld2_1, "chunk 1"); /* Check vld3_dup/vld3q_dup. */ clean_results (); #undef TEST_MSG #define TEST_MSG "VLD3_DUP/VLD3Q_DUP" TEST_ALL_VLDX_DUP(3); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_0, "chunk 0"); + CHECK_RESULTS_VLDX_DUP (TEST_MSG, expected_vld3_0, "chunk 0"); TEST_ALL_EXTRA_CHUNKS(3, 1); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_1, "chunk 1"); + CHECK_RESULTS_VLDX_DUP (TEST_MSG, expected_vld3_1, "chunk 1"); TEST_ALL_EXTRA_CHUNKS(3, 2); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_2, "chunk 2"); + CHECK_RESULTS_VLDX_DUP (TEST_MSG, expected_vld3_2, "chunk 2"); /* Check vld4_dup/vld4q_dup */ clean_results (); #undef TEST_MSG #define TEST_MSG "VLD4_DUP/VLD4Q_DUP" TEST_ALL_VLDX_DUP(4); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_0, "chunk 0"); + CHECK_RESULTS_VLDX_DUP (TEST_MSG, expected_vld4_0, "chunk 0"); TEST_ALL_EXTRA_CHUNKS(4, 1); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_1, "chunk 1"); + CHECK_RESULTS_VLDX_DUP (TEST_MSG, expected_vld4_1, "chunk 1"); TEST_ALL_EXTRA_CHUNKS(4, 2); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_2, "chunk 2"); + CHECK_RESULTS_VLDX_DUP (TEST_MSG, expected_vld4_2, "chunk 2"); TEST_ALL_EXTRA_CHUNKS(4, 3); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_3, "chunk 3"); + CHECK_RESULTS_VLDX_DUP (TEST_MSG, expected_vld4_3, "chunk 3"); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c index 1991033..2f2e62f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c @@ -9,42 +9,24 @@ VECT_VAR_DECL(expected_vld2_0,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld2_0,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected_vld2_0,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld2_0,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld2_0,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_0,uint,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; -VECT_VAR_DECL(expected_vld2_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_0,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld2_0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld2_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld2_0,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld2_0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, @@ -55,40 +37,22 @@ VECT_VAR_DECL(expected_vld2_1,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf1 }; VECT_VAR_DECL(expected_vld2_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_1,int,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld2_1,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld2_1,uint,8,8) [] = { 0xf0, 0xf1, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld2_1,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xfff0, 0xfff1 }; VECT_VAR_DECL(expected_vld2_1,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected_vld2_1,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xfff0, 0xfff1 }; VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld2_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld2_1,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0, 0xfff1, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_1,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld2_1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld2_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld2_1,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xfff0, 0xfff1, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_1,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld2_1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld2_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld2_1,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xfff0, 0xfff1, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_1,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, @@ -99,40 +63,22 @@ VECT_VAR_DECL(expected_vld3_0,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld3_0,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected_vld3_0,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_0,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld3_0,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_0,uint,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld3_0,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_0,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld3_0,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; -VECT_VAR_DECL(expected_vld3_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld3_0,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_0,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld3_0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld3_0,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld3_0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld3_0,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_0,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, @@ -143,40 +89,22 @@ VECT_VAR_DECL(expected_vld3_1,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld3_1,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xfff0, 0xfff1 }; VECT_VAR_DECL(expected_vld3_1,int,32,2) [] = { 0xfffffff2, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld3_1,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_1,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf1, 0xf2, 0xaa }; VECT_VAR_DECL(expected_vld3_1,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_1,uint,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 }; -VECT_VAR_DECL(expected_vld3_1,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_1,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf1, 0xf2, 0xaa }; VECT_VAR_DECL(expected_vld3_1,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_1,hfloat,32,2) [] = { 0xc1600000, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld3_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld3_1,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_1,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected_vld3_1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld3_1,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 }; VECT_VAR_DECL(expected_vld3_1,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld3_1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld3_1,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 }; VECT_VAR_DECL(expected_vld3_1,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, @@ -187,40 +115,22 @@ VECT_VAR_DECL(expected_vld3_2,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf1, 0xf2 }; VECT_VAR_DECL(expected_vld3_2,int,16,4) [] = { 0xfff2, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_2,int,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld3_2,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_2,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld3_2,uint,16,4) [] = { 0xaaaa, 0xfff0, 0xfff1, 0xfff2 }; VECT_VAR_DECL(expected_vld3_2,uint,32,2) [] = { 0xfffffff1, 0xfffffff2 }; -VECT_VAR_DECL(expected_vld3_2,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld3_2,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld3_2,poly,16,4) [] = { 0xaaaa, 0xfff0, 0xfff1, 0xfff2 }; VECT_VAR_DECL(expected_vld3_2,hfloat,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld3_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld3_2,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xfff0, 0xfff1, 0xfff2, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_2,int,32,4) [] = { 0xfffffff2, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld3_2,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld3_2,uint,16,8) [] = { 0xfff1, 0xfff2, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_2,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld3_2,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld3_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld3_2,poly,16,8) [] = { 0xfff1, 0xfff2, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_2,hfloat,32,4) [] = { 0xc1600000, 0xaaaaaaaa, @@ -231,40 +141,22 @@ VECT_VAR_DECL(expected_vld4_0,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_0,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected_vld4_0,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_0,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_0,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_0,uint,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_0,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_0,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_0,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; -VECT_VAR_DECL(expected_vld4_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_0,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_0,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_0,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected_vld4_0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_0,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_0,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, @@ -275,40 +167,22 @@ VECT_VAR_DECL(expected_vld4_1,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_1,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_1,int,32,2) [] = { 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected_vld4_1,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_1,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_1,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_1,uint,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_1,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_1,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_1,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; -VECT_VAR_DECL(expected_vld4_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_1,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_1,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_1,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_1,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_1,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_1,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, @@ -319,40 +193,22 @@ VECT_VAR_DECL(expected_vld4_2,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_2,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected_vld4_2,int,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_2,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_2,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_2,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_2,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected_vld4_2,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_2,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_2,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_2,hfloat,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_2,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_2,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected_vld4_2,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_2,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected_vld4_2,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_2,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_2,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected_vld4_2,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, @@ -363,40 +219,22 @@ VECT_VAR_DECL(expected_vld4_3,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf1, 0xf2, 0xf3 }; VECT_VAR_DECL(expected_vld4_3,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_3,int,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_3,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_3,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_3,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected_vld4_3,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected_vld4_3,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected_vld4_3,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_3,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected_vld4_3,hfloat,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_3,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_3,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_3,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_3,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_3,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_3,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_3,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; -VECT_VAR_DECL(expected_vld4_3,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected_vld4_3,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected_vld4_3,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_3,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, @@ -542,6 +380,26 @@ void exec_vldX_lane (void) TEST_EXTRA_CHUNK(float, 32, 2, X, Y); \ TEST_EXTRA_CHUNK(float, 32, 4, X, Y) + /* vldX_lane supports only a subset of all variants. */ +#define CHECK_RESULTS_VLDX_LANE(test_name,EXPECTED,comment) \ + { \ + CHECK(test_name, int, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, int, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK(test_name, int, 32, 2, PRIx32, EXPECTED, comment); \ + CHECK(test_name, uint, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment); \ + CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment); \ + CHECK(test_name, int, 16, 8, PRIx16, EXPECTED, comment); \ + CHECK(test_name, int, 32, 4, PRIx32, EXPECTED, comment); \ + CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment); \ + CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment); \ + CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment); \ + CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment); \ + } \ + /* Declare the temporary buffers / variables. */ DECL_ALL_VLDX_LANE(2); DECL_ALL_VLDX_LANE(3); @@ -568,39 +426,39 @@ void exec_vldX_lane (void) clean_results (); #define TEST_MSG "VLD2_LANE/VLD2Q_LANE" TEST_ALL_VLDX_LANE(2); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_0, " chunk 0"); + CHECK_RESULTS_VLDX_LANE (TEST_MSG, expected_vld2_0, " chunk 0"); TEST_ALL_EXTRA_CHUNKS(2, 1); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_1, " chunk 1"); + CHECK_RESULTS_VLDX_LANE (TEST_MSG, expected_vld2_1, " chunk 1"); /* Check vld3_lane/vld3q_lane. */ clean_results (); #undef TEST_MSG #define TEST_MSG "VLD3_LANE/VLD3Q_LANE" TEST_ALL_VLDX_LANE(3); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_0, " chunk 0"); + CHECK_RESULTS_VLDX_LANE (TEST_MSG, expected_vld3_0, " chunk 0"); TEST_ALL_EXTRA_CHUNKS(3, 1); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_1, " chunk 1"); + CHECK_RESULTS_VLDX_LANE (TEST_MSG, expected_vld3_1, " chunk 1"); TEST_ALL_EXTRA_CHUNKS(3, 2); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_2, " chunk 2"); + CHECK_RESULTS_VLDX_LANE (TEST_MSG, expected_vld3_2, " chunk 2"); /* Check vld4_lane/vld4q_lane. */ clean_results (); #undef TEST_MSG #define TEST_MSG "VLD4_LANE/VLD4Q_LANE" TEST_ALL_VLDX_LANE(4); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_0, " chunk 0"); + CHECK_RESULTS_VLDX_LANE (TEST_MSG, expected_vld4_0, " chunk 0"); TEST_ALL_EXTRA_CHUNKS(4, 1); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_1, " chunk 1"); + CHECK_RESULTS_VLDX_LANE (TEST_MSG, expected_vld4_1, " chunk 1"); TEST_ALL_EXTRA_CHUNKS(4, 2); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_2, " chunk 2"); + CHECK_RESULTS_VLDX_LANE (TEST_MSG, expected_vld4_2, " chunk 2"); TEST_ALL_EXTRA_CHUNKS(4, 3); - CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_3, " chunk 3"); + CHECK_RESULTS_VLDX_LANE (TEST_MSG, expected_vld4_3, " chunk 3"); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c index 7527861..0cbb656 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c @@ -7,15 +7,12 @@ VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0x1, 0x12, 0x23, 0x34, 0x45, 0x56, 0x67 }; VECT_VAR_DECL(expected,int,16,4) [] = { 0xfde0, 0xfe02, 0xfe24, 0xfe46 }; VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffcd0, 0xfffffd03 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0xc0, 0x4, 0x48, 0x8c, 0xd0, 0x14, 0x58, 0x9c }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfab0, 0xfb05, 0xfb5a, 0xfbaf }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffff9a0, 0xfffffa06 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0xc0, 0x84, 0x48, 0xc, 0xd0, 0x94, 0x58, 0x1c }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc4053333, 0xc3f9c000 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x90, 0x7, 0x7e, 0xf5, 0x6c, 0xe3, 0x5a, 0xd1, @@ -25,8 +22,6 @@ VECT_VAR_DECL(expected,int,16,8) [] = { 0xf780, 0xf808, 0xf890, 0xf918, 0xf9a0, 0xfa28, 0xfab0, 0xfb38 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffff670, 0xfffff709, 0xfffff7a2, 0xfffff83b }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,16) [] = { 0x60, 0xa, 0xb4, 0x5e, 0x8, 0xb2, 0x5c, 0x6, 0xb0, 0x5a, 0x4, 0xae, @@ -35,14 +30,10 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf450, 0xf50b, 0xf5c6, 0xf681, 0xf73c, 0xf7f7, 0xf8b2, 0xf96d }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffff340, 0xfffff40c, 0xfffff4d8, 0xfffff5a4 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected,poly,8,16) [] = { 0x60, 0xca, 0x34, 0x9e, 0xc8, 0x62, 0x9c, 0x36, 0x30, 0x9a, 0x64, 0xce, 0x98, 0x32, 0xcc, 0x66 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4c73333, 0xc4bac000, 0xc4ae4ccd, 0xc4a1d999 }; @@ -145,7 +136,22 @@ void FNNAME (INSN_NAME) (void) TEST_VMUL(INSN_NAME, q, poly, p, 8, 16); TEST_VMUL(INSN_NAME, q, float, f, 32, 4); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c index c45492d..78f17ed 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c @@ -12,41 +12,11 @@ VECT_VAR_DECL(expected,int,8,8) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9 }; VECT_VAR_DECL(expected,int,16,4) [] = { 0x10, 0xf, 0xe, 0xd }; VECT_VAR_DECL(expected,int,32,2) [] = { 0x10, 0xf }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results for float32 variants. Needs to be separated since the generic test function does not test floating-point diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vorn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vorn.c index 6905cb6..d1674733 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vorn.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vorn.c @@ -14,10 +14,6 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xfb, 0xfb, 0xfb, 0xfb, VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff3, 0xfff3 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff7, 0xfffffff7 }; VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffffd }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xf9, 0xf9, 0xfb, 0xfb, 0xfd, 0xfd, 0xff, 0xff, 0xf9, 0xf9, 0xfb, 0xfb, @@ -38,11 +34,3 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff8, 0xfffffff9, 0xfffffffa, 0xfffffffb }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffffc, 0xfffffffffffffffd }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vorr.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vorr.c index b2a7dff..4948964 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vorr.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vorr.c @@ -14,10 +14,6 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf4, 0xf5, 0xf6, 0xf7, VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfffe, 0xffff, 0xfffe, 0xffff }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff8, 0xfffffff9 }; VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff2 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xf6, 0xf7, 0xf6, 0xf7, 0xf6, 0xf7, 0xf6, 0xf7, 0xfe, 0xff, 0xfe, 0xff, @@ -38,11 +34,3 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff7, 0xfffffff7, 0xfffffff7, 0xfffffff7 }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff3, 0xfffffffffffffff3 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c index f2be790..4a7ab17 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c @@ -11,16 +11,6 @@ void vqabs_extra(void); VECT_VAR_DECL(expected,int,8,8) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9 }; VECT_VAR_DECL(expected,int,16,4) [] = { 0x10, 0xf, 0xe, 0xd }; VECT_VAR_DECL(expected,int,32,2) [] = { 0x10, 0xf }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x5, @@ -28,25 +18,6 @@ VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected values of cumulative_saturation flag. */ int VECT_VAR(expected_cumulative_sat,int,8,8) = 0; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqadd.c index c07f5ff..eaa6e82 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqadd.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqadd.c @@ -39,10 +39,6 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected,uint,64,1) [] = { 0xffffffffffffffff }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, @@ -61,14 +57,6 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffffff, 0xffffffffffffffff }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* 64-bits types, with 0 as second input. */ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c index 942eba8..21a0926 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c @@ -11,16 +11,6 @@ void vqneg_extra(void); VECT_VAR_DECL(expected,int,8,8) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9 }; VECT_VAR_DECL(expected,int,16,4) [] = { 0x10, 0xf, 0xe, 0xd }; VECT_VAR_DECL(expected,int,32,2) [] = { 0x10, 0xf }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x5, @@ -28,25 +18,6 @@ VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected values of cumulative_saturation flag. */ int VECT_VAR(expected_cumulative_sat,int,8,8) = 0; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqsub.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqsub.c index 04df5fe..3068d4b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqsub.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqsub.c @@ -25,10 +25,6 @@ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xff8a, 0xff8b, 0xff8c, 0xff8d }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffff79, 0xffffff7a }; VECT_VAR_DECL(expected,uint,64,1) [] = { 0xffffffffffffff68 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xdf, 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, @@ -49,14 +45,6 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffff79, 0xffffff7a, 0xffffff7b, 0xffffff7c }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffff68, 0xffffffffffffff69 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected values of cumulative saturation flag. */ int VECT_VAR(expected_cumulative_sat,int,8,8) = 0; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc index 32c0d86..fec90b2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc @@ -68,7 +68,24 @@ void FNNAME (INSN_NAME) (void) TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 3); TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 12); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, ""); #ifdef EXTRA_TESTS EXTRA_TESTS(); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c index e64d6e3..821c11e 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c @@ -13,11 +13,6 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe0, 0xe2, 0xe4, 0xe6, VECT_VAR_DECL(expected,uint,16,4) [] = { 0xff80, 0xff88, 0xff90, 0xff98 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffff000, 0xfffff100 }; VECT_VAR_DECL(expected,uint,64,1) [] = { 0xffffffffffffff80 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, - 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0, 0xc0, 0xe0, 0x0, 0x20, 0x40, 0x60, @@ -36,14 +31,6 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0x0, 0x1000, 0x2000, 0x3000, VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x40000000, 0x80000000, 0xc0000000 }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0x0, 0x8000000000000000 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results with large shift amount. */ VECT_VAR_DECL(expected_large_shift,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, @@ -56,11 +43,6 @@ VECT_VAR_DECL(expected_large_shift,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0, VECT_VAR_DECL(expected_large_shift,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; VECT_VAR_DECL(expected_large_shift,uint,32,2) [] = { 0x0, 0x0 }; VECT_VAR_DECL(expected_large_shift,uint,64,1) [] = { 0x0 }; -VECT_VAR_DECL(expected_large_shift,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_large_shift,poly,16,4) [] = { 0x3333, 0x3333, - 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_large_shift,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected_large_shift,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -77,16 +59,6 @@ VECT_VAR_DECL(expected_large_shift,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; VECT_VAR_DECL(expected_large_shift,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; VECT_VAR_DECL(expected_large_shift,uint,64,2) [] = { 0x0, 0x0 }; -VECT_VAR_DECL(expected_large_shift,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_large_shift,poly,16,8) [] = { 0x3333, 0x3333, - 0x3333, 0x3333, - 0x3333, 0x3333, - 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_large_shift,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results with negative shift amount. */ @@ -103,12 +75,6 @@ VECT_VAR_DECL(expected_negative_shift,uint,16,4) [] = { 0x7ff8, 0x7ff8, VECT_VAR_DECL(expected_negative_shift,uint,32,2) [] = { 0x3ffffffc, 0x3ffffffc }; VECT_VAR_DECL(expected_negative_shift,uint,64,1) [] = { 0xfffffffffffffff }; -VECT_VAR_DECL(expected_negative_shift,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_negative_shift,poly,16,4) [] = { 0x3333, 0x3333, - 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_negative_shift,hfloat,32,2) [] = { 0x33333333, - 0x33333333 }; VECT_VAR_DECL(expected_negative_shift,int,8,16) [] = { 0xfc, 0xfc, 0xfc, 0xfc, 0xfd, 0xfd, 0xfd, 0xfd, 0xfe, 0xfe, 0xfe, 0xfe, @@ -133,18 +99,6 @@ VECT_VAR_DECL(expected_negative_shift,uint,32,4) [] = { 0x1ffffffe, 0x1ffffffe, 0x1ffffffe, 0x1ffffffe }; VECT_VAR_DECL(expected_negative_shift,uint,64,2) [] = { 0x7ffffffffffffff, 0x7ffffffffffffff }; -VECT_VAR_DECL(expected_negative_shift,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected_negative_shift,poly,16,8) [] = { 0x3333, 0x3333, - 0x3333, 0x3333, - 0x3333, 0x3333, - 0x3333, 0x3333 }; -VECT_VAR_DECL(expected_negative_shift,hfloat,32,4) [] = { 0x33333333, - 0x33333333, - 0x33333333, - 0x33333333 }; #ifndef INSN_NAME @@ -187,7 +141,22 @@ void FNNAME (INSN_NAME) (void) /* Execute the tests. */ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VSHL, int); - CHECK_RESULTS (TEST_MSG, ""); + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); /* Test large shift amount (larger or equal to the type width. */ @@ -203,7 +172,23 @@ void FNNAME (INSN_NAME) (void) /* Execute the tests. */ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VSHL, int); - CHECK_RESULTS_NAMED (TEST_MSG, expected_large_shift, "(large shift amount)"); +#define COMMENT1 "(large shift amount)" + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_large_shift, COMMENT1); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_large_shift, COMMENT1); /* Test negative shift amount. */ @@ -219,7 +204,23 @@ void FNNAME (INSN_NAME) (void) /* Execute the tests. */ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VSHL, int); - CHECK_RESULTS_NAMED (TEST_MSG, expected_negative_shift, "(negative shift amount)"); +#define COMMENT2 "(negative shift amount)" + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_negative_shift, COMMENT2); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_negative_shift, COMMENT2); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc index 928f338..ad0b4ff 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc @@ -120,15 +120,40 @@ void FNNAME (INSN_NAME) (void) TEST_EXTRA_CHUNK(poly, 16, 8, 1); \ TEST_EXTRA_CHUNK(float, 32, 4, 1) + /* vshuffle support all vector types except [u]int64x1 and + [u]int64x2. */ +#define CHECK_RESULTS_VSHUFFLE(test_name,EXPECTED,comment) \ + { \ + CHECK(test_name, int, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, int, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK(test_name, int, 32, 2, PRIx32, EXPECTED, comment); \ + CHECK(test_name, uint, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment); \ + CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment); \ + CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment); \ + \ + CHECK(test_name, int, 8, 16, PRIx8, EXPECTED, comment); \ + CHECK(test_name, int, 16, 8, PRIx16, EXPECTED, comment); \ + CHECK(test_name, int, 32, 4, PRIx32, EXPECTED, comment); \ + CHECK(test_name, uint, 8, 16, PRIx8, EXPECTED, comment); \ + CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment); \ + CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment); \ + CHECK(test_name, poly, 8, 16, PRIx8, EXPECTED, comment); \ + CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment); \ + CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment); \ + } \ + clean_results (); /* Execute the tests. */ TEST_ALL_VSHUFFLE(INSN_NAME); - CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)"); + CHECK_RESULTS_VSHUFFLE (TEST_MSG, expected0, "(chunk 0)"); TEST_ALL_EXTRA_CHUNKS(); - CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)"); + CHECK_RESULTS_VSHUFFLE (TEST_MSG, expected1, "(chunk 1)"); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c index eb06ce0..0285083 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c @@ -23,7 +23,6 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0x10 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0x50, 0x51, 0x52, 0x53, 0x50, 0x51, 0x52, 0x53 }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0x7bf0, 0x7bf1, 0x7bf2, 0x7bf3 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, @@ -48,8 +47,6 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67 }; VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3ff0, 0x3ff1, 0x3ff2, 0x3ff3, 0x3ff4, 0x3ff5, 0x3ff6, 0x3ff7 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results with max shift amount. */ VECT_VAR_DECL(expected_max_shift,int,8,8) [] = { 0x70, 0x71, 0x72, 0x73, @@ -68,7 +65,6 @@ VECT_VAR_DECL(expected_max_shift,poly,8,8) [] = { 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77 }; VECT_VAR_DECL(expected_max_shift,poly,16,4) [] = { 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3 }; -VECT_VAR_DECL(expected_max_shift,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected_max_shift,int,8,16) [] = { 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, @@ -95,8 +91,6 @@ VECT_VAR_DECL(expected_max_shift,poly,8,16) [] = { 0x70, 0x71, 0x72, 0x73, 0x7c, 0x7d, 0x7e, 0x7f }; VECT_VAR_DECL(expected_max_shift,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; -VECT_VAR_DECL(expected_max_shift,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #include "vsXi_n.inc" @@ -158,5 +152,23 @@ void vsli_extra(void) TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 7); TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 15); - CHECK_RESULTS_NAMED (TEST_MSG, expected_max_shift, "(max shift amount)"); +#define COMMENT "(max shift amount)" + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_shift, COMMENT); + CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shift, COMMENT); + CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c index 046b79f..5f05314 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c @@ -23,7 +23,6 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xe000000000000000 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0xc5, 0xc5, 0xc5, 0xc5, 0xc5, 0xc5, 0xc5, 0xc5 }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xffc0, 0xffc0, 0xffc0, 0xffc0 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xf7, 0xf7, 0xf7, 0xf7, 0xf7, 0xf7, 0xf7, 0xf7, 0xff, 0xff, 0xff, 0xff, @@ -50,8 +49,6 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xe1, 0xe1, 0xe1, 0xe1, 0xe1, 0xe1, 0xe1, 0xe1 }; VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0, 0xfff0, 0xfff0, 0xfff0, 0xfff0 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results with max shift amount. */ VECT_VAR_DECL(expected_max_shift,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, @@ -70,7 +67,6 @@ VECT_VAR_DECL(expected_max_shift,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; VECT_VAR_DECL(expected_max_shift,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; -VECT_VAR_DECL(expected_max_shift,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected_max_shift,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, @@ -97,8 +93,6 @@ VECT_VAR_DECL(expected_max_shift,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xfc, 0xfd, 0xfe, 0xff }; VECT_VAR_DECL(expected_max_shift,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; -VECT_VAR_DECL(expected_max_shift,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #include "vsXi_n.inc" @@ -160,5 +154,23 @@ void vsri_extra(void) TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 8); TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 16); - CHECK_RESULTS_NAMED (TEST_MSG, expected_max_shift, "(max shift amount)"); +#define COMMENT "(max shift amount)" + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_shift, COMMENT); + CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_shift, COMMENT); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shift, COMMENT); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shift, COMMENT); + CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT); + CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c index 7620479..1a108d5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c @@ -18,10 +18,6 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xdc, 0xdd, 0xde, 0xdf, VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffd2, 0xffd3, 0xffd4, 0xffd5 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffc8, 0xffffffc9 }; VECT_VAR_DECL(expected,uint,64,1) [] = { 0xffffffffffffffee }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, @@ -41,14 +37,6 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffb9, 0xffffffba, 0xffffffbb, 0xffffffbc }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffffed, 0xffffffffffffffee }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; /* Expected results for float32 variants. Needs to be separated since the generic test function does not test floating-point diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c index b765b2b..840b489 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c @@ -6,43 +6,13 @@ #define TEST_MSG "VSUBL" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0, 0x1, 0x2, 0x3, 0x4 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffe, 0xffffffff, 0x0, 0x1 }; VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x1 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0, 0x1, 0x2, 0x3, 0x4 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0x0, 0x1, 0x2 }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0x0, 0x1 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #include "vXXXl.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c index 3e8bc98..7de1fe9 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c @@ -6,45 +6,15 @@ #define TEST_MSG "VSUBW" /* Expected results. */ -VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0, 0x1, 0x2, 0x3, 0x4 }; VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffe, 0xffffffff, 0x0, 0x1 }; VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x1 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfefd, 0xfefe, 0xfeff, 0xff00, 0xff01, 0xff02, 0xff03, 0xff04 }; VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffeffff, 0xffff0000, 0xffff0001, 0xffff0002 }; VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffff00000000, 0xffffffff00000001 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; #include "vXXXw.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c index be18c0f..2c4a09c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c @@ -8,12 +8,10 @@ VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11, 0xf2, 0xf3, 0x11, 0x11 }; VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 }; VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected0,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, 0xf2, 0xf3, 0x55, 0x55 }; VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 }; VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected0,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, 0xf2, 0xf3, 0x55, 0x55 }; VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 }; @@ -25,8 +23,6 @@ VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11, VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, 0x22, 0x22, 0xfff2, 0xfff3, 0x22, 0x22 }; VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x33, 0x33 }; -VECT_VAR_DECL(expected0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, 0xf2, 0xf3, 0x55, 0x55, 0xf4, 0xf5, 0x55, 0x55, @@ -34,8 +30,6 @@ VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66, 0xfff2, 0xfff3, 0x66, 0x66 }; VECT_VAR_DECL(expected0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x77, 0x77 }; -VECT_VAR_DECL(expected0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, 0xf2, 0xf3, 0x55, 0x55, 0xf4, 0xf5, 0x55, 0x55, @@ -50,12 +44,10 @@ VECT_VAR_DECL(expected1,int,8,8) [] = { 0xf4, 0xf5, 0x11, 0x11, 0xf6, 0xf7, 0x11, 0x11 }; VECT_VAR_DECL(expected1,int,16,4) [] = { 0xfff2, 0xfff3, 0x22, 0x22 }; VECT_VAR_DECL(expected1,int,32,2) [] = { 0x33, 0x33 }; -VECT_VAR_DECL(expected1,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected1,uint,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55, 0xf6, 0xf7, 0x55, 0x55 }; VECT_VAR_DECL(expected1,uint,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 }; VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 }; -VECT_VAR_DECL(expected1,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55, 0xf6, 0xf7, 0x55, 0x55 }; VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 }; @@ -67,8 +59,6 @@ VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf8, 0xf9, 0x11, 0x11, VECT_VAR_DECL(expected1,int,16,8) [] = { 0xfff4, 0xfff5, 0x22, 0x22, 0xfff6, 0xfff7, 0x22, 0x22 }; VECT_VAR_DECL(expected1,int,32,4) [] = { 0xfffffff2, 0xfffffff3, 0x33, 0x33 }; -VECT_VAR_DECL(expected1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected1,uint,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55, 0xfa, 0xfb, 0x55, 0x55, 0xfc, 0xfd, 0x55, 0x55, @@ -76,8 +66,6 @@ VECT_VAR_DECL(expected1,uint,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55, VECT_VAR_DECL(expected1,uint,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66, 0xfff6, 0xfff7, 0x66, 0x66 }; VECT_VAR_DECL(expected1,uint,32,4) [] = { 0xfffffff2, 0xfffffff3, 0x77, 0x77 }; -VECT_VAR_DECL(expected1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55, 0xfa, 0xfb, 0x55, 0x55, 0xfc, 0xfd, 0x55, 0x55, diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c index ec9ded3..ab6e576 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c @@ -9,14 +9,12 @@ VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected0,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected0,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, @@ -32,8 +30,6 @@ VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff6, 0xfff7 }; VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, @@ -44,8 +40,6 @@ VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff6, 0xfff7 }; VECT_VAR_DECL(expected0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; -VECT_VAR_DECL(expected0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, @@ -62,12 +56,10 @@ VECT_VAR_DECL(expected1,int,8,8) [] = { 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11 }; VECT_VAR_DECL(expected1,int,16,4) [] = { 0x22, 0x22, 0x22, 0x22 }; VECT_VAR_DECL(expected1,int,32,2) [] = { 0x33, 0x33 }; -VECT_VAR_DECL(expected1,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected1,uint,8,8) [] = { 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55 }; VECT_VAR_DECL(expected1,uint,16,4) [] = { 0x66, 0x66, 0x66, 0x66 }; VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 }; -VECT_VAR_DECL(expected1,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected1,poly,8,8) [] = { 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55 }; VECT_VAR_DECL(expected1,poly,16,4) [] = { 0x66, 0x66, 0x66, 0x66 }; @@ -79,8 +71,6 @@ VECT_VAR_DECL(expected1,int,8,16) [] = { 0x11, 0x11, 0x11, 0x11, VECT_VAR_DECL(expected1,int,16,8) [] = { 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22 }; VECT_VAR_DECL(expected1,int,32,4) [] = { 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected1,uint,8,16) [] = { 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, @@ -88,8 +78,6 @@ VECT_VAR_DECL(expected1,uint,8,16) [] = { 0x55, 0x55, 0x55, 0x55, VECT_VAR_DECL(expected1,uint,16,8) [] = { 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66 }; VECT_VAR_DECL(expected1,uint,32,4) [] = { 0x77, 0x77, 0x77, 0x77 }; -VECT_VAR_DECL(expected1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected1,poly,8,16) [] = { 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c index 05faa8a..b5fe516 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c @@ -9,13 +9,11 @@ VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, 0x22, 0x22 }; VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected0,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, 0xf1, 0xf5, 0x55, 0x55 }; VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, 0x66, 0x66 }; VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; -VECT_VAR_DECL(expected0,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, 0xf1, 0xf5, 0x55, 0x55 }; VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, @@ -29,8 +27,6 @@ VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff4, 0x22, 0x22, 0xfff1, 0xfff5, 0x22, 0x22 }; VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, 0x33, 0x33 }; -VECT_VAR_DECL(expected0,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf8, 0x55, 0x55, 0xf1, 0xf9, 0x55, 0x55, 0xf2, 0xfa, 0x55, 0x55, @@ -39,8 +35,6 @@ VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff4, 0x66, 0x66, 0xfff1, 0xfff5, 0x66, 0x66 }; VECT_VAR_DECL(expected0,uint,32,4) [] = { 0xfffffff0, 0xfffffff2, 0x77, 0x77 }; -VECT_VAR_DECL(expected0,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf8, 0x55, 0x55, 0xf1, 0xf9, 0x55, 0x55, 0xf2, 0xfa, 0x55, 0x55, @@ -56,13 +50,11 @@ VECT_VAR_DECL(expected1,int,8,8) [] = { 0xf2, 0xf6, 0x11, 0x11, VECT_VAR_DECL(expected1,int,16,4) [] = { 0xfff1, 0xfff3, 0x22, 0x22 }; VECT_VAR_DECL(expected1,int,32,2) [] = { 0x33, 0x33 }; -VECT_VAR_DECL(expected1,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected1,uint,8,8) [] = { 0xf2, 0xf6, 0x55, 0x55, 0xf3, 0xf7, 0x55, 0x55 }; VECT_VAR_DECL(expected1,uint,16,4) [] = { 0xfff1, 0xfff3, 0x66, 0x66 }; VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 }; -VECT_VAR_DECL(expected1,uint,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf2, 0xf6, 0x55, 0x55, 0xf3, 0xf7, 0x55, 0x55 }; VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff1, 0xfff3, @@ -76,8 +68,6 @@ VECT_VAR_DECL(expected1,int,16,8) [] = { 0xfff2, 0xfff6, 0x22, 0x22, 0xfff3, 0xfff7, 0x22, 0x22 }; VECT_VAR_DECL(expected1,int,32,4) [] = { 0xfffffff1, 0xfffffff3, 0x33, 0x33 }; -VECT_VAR_DECL(expected1,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected1,uint,8,16) [] = { 0xf4, 0xfc, 0x55, 0x55, 0xf5, 0xfd, 0x55, 0x55, 0xf6, 0xfe, 0x55, 0x55, @@ -86,8 +76,6 @@ VECT_VAR_DECL(expected1,uint,16,8) [] = { 0xfff2, 0xfff6, 0x66, 0x66, 0xfff3, 0xfff7, 0x66, 0x66 }; VECT_VAR_DECL(expected1,uint,32,4) [] = { 0xfffffff1, 0xfffffff3, 0x77, 0x77 }; -VECT_VAR_DECL(expected1,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf4, 0xfc, 0x55, 0x55, 0xf5, 0xfd, 0x55, 0x55, 0xf6, 0xfe, 0x55, 0x55,

[ARM,AArch64,testsuite] AdvSIMD intrinsics tests cleanup: remove useless expected values.

Commit Message

Patch