From patchwork Fri Oct 21 16:58:55 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Guittot X-Patchwork-Id: 4789 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 946D723DEF for ; Fri, 21 Oct 2011 16:59:07 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 7CC1EA182EB for ; Fri, 21 Oct 2011 16:59:07 +0000 (UTC) Received: by bkbzs2 with SMTP id zs2so7066352bkb.11 for ; Fri, 21 Oct 2011 09:59:07 -0700 (PDT) Received: by 10.223.4.215 with SMTP id 23mr25919916fas.8.1319216347123; Fri, 21 Oct 2011 09:59:07 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.1.71 with SMTP id 7cs22994lak; Fri, 21 Oct 2011 09:59:06 -0700 (PDT) Received: by 10.227.29.21 with SMTP id o21mr2134150wbc.87.1319216346357; Fri, 21 Oct 2011 09:59:06 -0700 (PDT) Received: from mail-wy0-f178.google.com (mail-wy0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id gg21si10190534wbb.10.2011.10.21.09.59.05 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 21 Oct 2011 09:59:06 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of vincent.guittot@linaro.org) client-ip=74.125.82.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of vincent.guittot@linaro.org) smtp.mail=vincent.guittot@linaro.org Received: by wyf28 with SMTP id 28so4822625wyf.37 for ; Fri, 21 Oct 2011 09:59:05 -0700 (PDT) Received: by 10.227.61.142 with SMTP id t14mr5877107wbh.68.1319216345677; Fri, 21 Oct 2011 09:59:05 -0700 (PDT) Received: from localhost.localdomain (pas72-1-88-161-60-229.fbx.proxad.net. [88.161.60.229]) by mx.google.com with ESMTPS id b5sm22863656wbh.4.2011.10.21.09.59.04 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 21 Oct 2011 09:59:04 -0700 (PDT) From: Vincent Guittot To: linaro-dev@lists.linaro.org Cc: patches@linaro.org, Vincent Guittot Subject: [RFC PATCH 07/11] ARM: cpu topology: Modify cpu_power according to cpufreq Date: Fri, 21 Oct 2011 18:58:55 +0200 Message-Id: <1319216335-2874-1-git-send-email-vincent.guittot@linaro.org> X-Mailer: git-send-email 1.7.4.1 Signed-off-by: Vincent Guittot --- arch/arm/kernel/topology.c | 75 +++++++++++++++++++++++++++++++++++++++----- 1 files changed, 67 insertions(+), 8 deletions(-) diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 1196f2d..9f75967 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -20,6 +20,10 @@ #include #include +#ifdef CONFIG_CPU_FREQ +#include +#endif + #include #include @@ -65,29 +69,35 @@ static DEFINE_PER_CPU(unsigned int, cpu_scale); struct cputopo_scale { int scale; + int freq; }; static struct cputopo_scale cpu_power[NR_CPUS]; -#define CPU_TOPO_MAX_SCALING 2 +#define CPU_MAX_SCALING 2 +#define CPU_MAX_FREQ 10 +/* we use a 200Mhz step for scaling cpu power */ +#define CPU_TOPO_FREQ_STEP 200000 #define ARM_CORTEX_A9_DEFAULT_SCALE 0 #define ARM_CORTEX_A9_POWER_SCALE 1 -/* This table sets the cpu_power scale of a cpu according to the sched_mc mode. - * The content of this table could be SoC specific so we should add a method to - * overwrite this default table. +/* This table sets the cpu_power scale of a cpu according to 2 inputs which are + * the frequency and the sched_mc mode. The content of this table could be SoC + * specific so we should add a method to overwrite this default table. * TODO: Study how to use DT for setting this table */ -static unsigned long table_cpu_power[CPU_TOPO_MAX_SCALING] = { - {1024}, /* default */ - {4096}, /* Power save mode CA9 MP */ +static unsigned long table_cpu_power[CPU_MAX_SCALING][CPU_MAX_FREQ] = { +/* 0 200 400 600 800 1000 1200 1400 1600 1800 */ + {1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024}, /* default */ + {4096, 4096, 4096, 1024, 1024, 1024, 1024, 1024, 1024, 1024}, /* Power save mode CA9 MP */ }; static void set_power_scale(unsigned int cpuid, unsigned int idx) { cpu_power[cpuid].scale = idx; - per_cpu(cpu_scale, cpuid) = table_cpu_power[cpu_power[cpuid].scale]; + per_cpu(cpu_scale, cpuid) = + table_cpu_power[idx][cpu_power[cpuid].freq]; smp_wmb(); } @@ -97,6 +107,54 @@ static int topo_cpuscale_init(void) return 0; } +#ifdef CONFIG_CPU_FREQ +static void set_cpufreq_scale(unsigned int cpuid, unsigned int idx) +{ + cpu_power[cpuid].freq = idx; + per_cpu(cpu_scale, cpuid) = + table_cpu_power[cpu_power[cpuid].scale][idx]; + smp_wmb(); +} + +static int topo_cpufreq_transition(struct notifier_block *nb, + unsigned long state, void *data) +{ + struct cpufreq_freqs *freqs = data; + + if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE) + set_cpufreq_scale(freqs->cpu, freqs->new / CPU_TOPO_FREQ_STEP); + + return NOTIFY_OK; +} + +static struct notifier_block topo_cpufreq_nb = { + .notifier_call = topo_cpufreq_transition, +}; + +static int topo_cpufreq_init(void) +{ + /* TODO set initial value according to current freq */ + + return cpufreq_register_notifier(&topo_cpufreq_nb, + CPUFREQ_TRANSITION_NOTIFIER); +} +#else +static inline int topo_cpufreq_init(void) {return 0; } +#endif + +static int init_cpu_power_scale(void) +{ + /* select cpu scale configuration */ + topo_cpuscale_init(); + + /* register cpufreq notifer */ + topo_cpufreq_init(); + + return 0; +} + +core_initcall(init_cpu_power_scale); + /* * Update the cpu power */ @@ -339,6 +397,7 @@ void init_cpu_topology(void) per_cpu(cpu_scale, cpu) = SCHED_POWER_SCALE; cpu_power[cpu].scale = ARM_CORTEX_A9_DEFAULT_SCALE; + cpu_power[cpu].freq = 0; } smp_wmb(); }