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[209.132.180.67]) by mx.google.com with ESMTP id ix6si17838787pac.46.2015.05.03.18.54.23; Sun, 03 May 2015 18:54:24 -0700 (PDT) Received-SPF: none (google.com: stable-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751783AbbEDByX (ORCPT + 2 others); Sun, 3 May 2015 21:54:23 -0400 Received: from mail-pa0-f44.google.com ([209.85.220.44]:36012 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751860AbbEDByW (ORCPT ); Sun, 3 May 2015 21:54:22 -0400 Received: by pabsx10 with SMTP id sx10so147755495pab.3 for ; Sun, 03 May 2015 18:54:22 -0700 (PDT) X-Received: by 10.68.173.66 with SMTP id bi2mr37629555pbc.5.1430704462263; Sun, 03 May 2015 18:54:22 -0700 (PDT) Received: from localhost ([180.150.153.1]) by mx.google.com with ESMTPSA id k3sm11046026pde.18.2015.05.03.18.54.20 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 03 May 2015 18:54:20 -0700 (PDT) From: shannon.zhao@linaro.org To: stable@vger.kernel.org Cc: gregkh@linuxfoundation.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org, Andre Przywara , Marc Zyngier Subject: [PATCH for 3.14.y stable 12/47] KVM: arm/arm64: vgic: fix GICD_ICFGR register accesses Date: Mon, 4 May 2015 09:52:07 +0800 Message-Id: <1430704362-6292-13-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1430704362-6292-1-git-send-email-shannon.zhao@linaro.org> References: <1430704362-6292-1-git-send-email-shannon.zhao@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: stable@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Andre Przywara commit f2ae85b2ab3776b9e4e42e5b6fa090f40d396794 upstream. Since KVM internally represents the ICFGR registers by stuffing two of them into one word, the offset for accessing the internal representation and the one for the MMIO based access are different. So keep the original offset around, but adjust the internal array offset by one bit. Reported-by: Haibin Wang Signed-off-by: Andre Przywara Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall Signed-off-by: Shannon Zhao --- virt/kvm/arm/vgic.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 26954a7..2f8aee5 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -548,11 +548,10 @@ static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu, u32 val; u32 *reg; - offset >>= 1; reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg, - vcpu->vcpu_id, offset); + vcpu->vcpu_id, offset >> 1); - if (offset & 2) + if (offset & 4) val = *reg >> 16; else val = *reg & 0xffff; @@ -561,13 +560,13 @@ static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu, vgic_reg_access(mmio, &val, offset, ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); if (mmio->is_write) { - if (offset < 4) { + if (offset < 8) { *reg = ~0U; /* Force PPIs/SGIs to 1 */ return false; } val = vgic_cfg_compress(val); - if (offset & 2) { + if (offset & 4) { *reg &= 0xffff; *reg |= val << 16; } else {