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[209.132.180.131]) by mx.google.com with ESMTPS id pd4si2346135pbb.70.2015.05.11.00.27.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 May 2015 00:27:52 -0700 (PDT) Received-SPF: pass (google.com: domain of gdb-patches-return-122771-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 29790 invoked by alias); 11 May 2015 07:27:25 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Subscribe: List-Archive: List-Post: , List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 29722 invoked by uid 89); 11 May 2015 07:27:24 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f179.google.com Received: from mail-wi0-f179.google.com (HELO mail-wi0-f179.google.com) (209.85.212.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Mon, 11 May 2015 07:27:20 +0000 Received: by wicmc15 with SMTP id mc15so21037141wic.1 for ; Mon, 11 May 2015 00:27:16 -0700 (PDT) X-Received: by 10.180.231.4 with SMTP id tc4mr17118691wic.27.1431329236824; Mon, 11 May 2015 00:27:16 -0700 (PDT) Received: from localhost.localdomain ([39.34.108.78]) by mx.google.com with ESMTPSA id gj7sm11843691wib.4.2015.05.11.00.27.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 11 May 2015 00:27:16 -0700 (PDT) From: Omair Javaid To: gdb-patches@sourceware.org Subject: [PATCH v5 4/6] Support for recording aarch64 advanced SIMD instructions Date: Mon, 11 May 2015 12:26:58 +0500 Message-Id: <1431329220-13019-5-git-send-email-omair.javaid@linaro.org> In-Reply-To: <1431329220-13019-1-git-send-email-omair.javaid@linaro.org> References: <1422967649-17436-1-git-send-email-omair.javaid@linaro.org> <1431329220-13019-1-git-send-email-omair.javaid@linaro.org> X-IsSubscribed: yes X-Original-Sender: omair.javaid@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::233 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@sourceware.org X-Google-Group-Id: 836684582541 I have updated this patch after suggested changes. I have made some updated though most of code seemed to follow the manual. I will reply to questions on last review message separately. gdb: 2015-05-11 Omair Javaid * aarch64-tdep.c (aarch64_record_data_proc_simd_fp): New function. (aarch64_record_asimd_load_store): New function. (aarch64_record_load_store): Install record handler aarch64_record_asimd_load_store. (aarch64_record_decode_insn_handler): Install record handler aarch64_record_data_proc_simd_fp. --- gdb/aarch64-tdep.c | 257 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 255 insertions(+), 2 deletions(-) diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 9905552..365c2d0 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -2943,6 +2943,7 @@ aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r) } /* Record handler for data processing - immediate instructions. */ + static unsigned int aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r) { @@ -2988,6 +2989,7 @@ aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r) } /* Record handler for branch, exception generation and system instructions. */ + static unsigned int aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r) { @@ -3064,7 +3066,168 @@ aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r) return AARCH64_RECORD_SUCCESS; } +/* Record handler for advanced SIMD load and store instructions. */ + +static unsigned int +aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r) +{ + CORE_ADDR address; + uint64_t addr_offset = 0; + uint32_t record_buf[24]; + uint64_t record_buf_mem[24]; + uint32_t reg_rn, reg_rt; + uint32_t reg_index = 0, mem_index = 0; + uint8_t opcode_bits, size_bits; + + reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); + reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); + size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11); + opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15); + regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address); + + /* Load/store single structure. */ + if (bit (aarch64_insn_r->aarch64_insn, 24)) + { + uint8_t sindex, scale, selem, esize, replicate = 0; + scale = opcode_bits >> 2; + selem = ((opcode_bits & 0x02) | + bit (aarch64_insn_r->aarch64_insn, 21)) + 1; + switch (scale) + { + case 1: + if (size_bits & 0x01) + return AARCH64_RECORD_UNKNOWN; + break; + case 2: + if ((size_bits >> 1) & 0x01) + return AARCH64_RECORD_UNKNOWN; + if (size_bits & 0x01) + { + if (!((opcode_bits >> 1) & 0x01)) + scale = 3; + else + return AARCH64_RECORD_UNKNOWN; + } + break; + case 3: + if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01)) + { + scale = size_bits; + replicate = 1; + break; + } + else + return AARCH64_RECORD_UNKNOWN; + default: + break; + } + esize = 8 << scale; + if (replicate) + for (sindex = 0; sindex < selem; sindex++) + { + record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; + reg_rt = (reg_rt + 1) % 32; + } + else + { + for (sindex = 0; sindex < selem; sindex++) + if (bit (aarch64_insn_r->aarch64_insn, 22)) + record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; + else + { + record_buf_mem[mem_index++] = esize / 8; + record_buf_mem[mem_index++] = address + addr_offset; + } + addr_offset = addr_offset + (esize / 8); + reg_rt = (reg_rt + 1) % 32; + } + } + /* Load/store multiple structure. */ + else + { + uint8_t selem, esize, rpt, elements; + uint8_t eindex, rindex; + esize = 8 << size_bits; + if (bit (aarch64_insn_r->aarch64_insn, 30)) + elements = 128 / esize; + else + elements = 64 / esize; + + switch (opcode_bits) + { + /*LD/ST4 (4 Registers). */ + case 0: + rpt = 1; + selem = 4; + break; + /*LD/ST1 (4 Registers). */ + case 2: + rpt = 4; + selem = 1; + break; + /*LD/ST3 (3 Registers). */ + case 4: + rpt = 1; + selem = 3; + break; + /*LD/ST1 (3 Registers). */ + case 6: + rpt = 3; + selem = 1; + break; + /*LD/ST1 (1 Register). */ + case 7: + rpt = 1; + selem = 1; + break; + /*LD/ST2 (2 Registers). */ + case 8: + rpt = 1; + selem = 2; + break; + /*LD/ST1 (2 Registers). */ + case 10: + rpt = 2; + selem = 1; + break; + default: + return AARCH64_RECORD_UNSUPPORTED; + break; + } + for (rindex = 0; rindex < rpt; rindex++) + for (eindex = 0; eindex < elements; eindex++) + { + uint8_t reg_tt, sindex; + reg_tt = (reg_rt + rindex) % 32; + for (sindex = 0; sindex < selem; sindex++) + { + if (bit (aarch64_insn_r->aarch64_insn, 22)) + record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM; + else + { + record_buf_mem[mem_index++] = esize / 8; + record_buf_mem[mem_index++] = address + addr_offset; + } + addr_offset = addr_offset + (esize / 8); + reg_tt = (reg_tt + 1) % 32; + } + } + } + + if (bit (aarch64_insn_r->aarch64_insn, 23)) + record_buf[reg_index++] = reg_rn; + + aarch64_insn_r->reg_rec_count = reg_index; + aarch64_insn_r->mem_rec_count = mem_index / 2; + MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, + record_buf_mem); + REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, + record_buf); + return AARCH64_RECORD_SUCCESS; +} + /* Record handler for load and store instructions. */ + static unsigned int aarch64_record_load_store (insn_decode_record *aarch64_insn_r) { @@ -3302,7 +3465,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r) } /* Advanced SIMD load/store instructions. */ else - return AARCH64_RECORD_UNSUPPORTED; + return aarch64_record_asimd_load_store (aarch64_insn_r); MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, record_buf_mem); @@ -3310,6 +3473,96 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r) record_buf); return AARCH64_RECORD_SUCCESS; } + +/* Record handler for data processing SIMD and floating point instructions. */ + +static unsigned int +aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r) +{ + uint8_t insn_bit21, opcode, rmode, reg_rd; + uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15; + uint8_t insn_bits11_14; + uint32_t record_buf[2]; + + insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); + insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); + insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); + insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15); + insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14); + opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18); + rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20); + reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); + insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); + + if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e) + { + /* Floating point - fixed point conversion instructions. */ + if (!insn_bit21) + { + if ((opcode >> 1) == 0x0 && rmode == 0x03) + record_buf[0] = reg_rd; + else + record_buf[0] = reg_rd + AARCH64_V0_REGNUM; + } + /* Floating point - conditional compare instructions. */ + else if (insn_bits10_11 == 0x01) + record_buf[0] = AARCH64_CPSR_REGNUM; + /* Floating point - data processing (2-source) and + conditional select instructions. */ + else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03) + record_buf[0] = reg_rd + AARCH64_V0_REGNUM; + else if (insn_bits10_11 == 0x00) + { + /* Floating point - immediate instructions. */ + if ((insn_bits12_15 & 0x01) == 0x01 || (insn_bits12_15 & 0x07) == 0x04) + record_buf[0] = reg_rd + AARCH64_V0_REGNUM; + /* Floating point - compare instructions. */ + else if ((insn_bits12_15 & 0x03) == 0x02) + record_buf[0] = AARCH64_CPSR_REGNUM; + /* Floating point - integer conversions instructions. */ + if (insn_bits12_15 == 0x00) + { + /* Convert float to integer instruction. */ + if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode)) + record_buf[0] = reg_rd + AARCH64_X0_REGNUM; + /* Convert integer to float instruction. */ + else if ((opcode >> 1) == 0x01 && !rmode) + record_buf[0] = reg_rd + AARCH64_V0_REGNUM; + /* Move float to integer instruction. */ + else if ((opcode >> 1) == 0x03) + { + if (!(opcode & 0x01)) + record_buf[0] = reg_rd + AARCH64_X0_REGNUM; + else + record_buf[0] = reg_rd + AARCH64_V0_REGNUM; + } + } + } + } + else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e) + { + /* Advanced SIMD copy instructions. */ + if (!bits (aarch64_insn_r->aarch64_insn, 21, 23) + && !bit (aarch64_insn_r->aarch64_insn, 15) + && bit (aarch64_insn_r->aarch64_insn, 10)) + { + if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07) + record_buf[0] = reg_rd + AARCH64_X0_REGNUM; + else + record_buf[0] = reg_rd + AARCH64_V0_REGNUM; + } + else + record_buf[0] = reg_rd + AARCH64_V0_REGNUM; + } + /* All remaining floating point or advanced SIMD instructions. */ + else + record_buf[0] = reg_rd + AARCH64_V0_REGNUM; + + REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, + record_buf); + return AARCH64_RECORD_SUCCESS; +} + /* Decodes insns type and invokes its record handler. */ static unsigned int @@ -3340,7 +3593,7 @@ aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r) /* Data processing - SIMD and floating point instructions. */ if (ins_bit25 && ins_bit26 && ins_bit27) - return AARCH64_RECORD_UNSUPPORTED; + return aarch64_record_data_proc_simd_fp (aarch64_insn_r); return AARCH64_RECORD_UNSUPPORTED; }