[3/6] ARM: hi6220: Add register and bitfield definition header files.

Message ID 1431437912-18988-4-git-send-email-peter.griffin@linaro.org
State New
Headers show

Commit Message

Peter Griffin May 12, 2015, 1:38 p.m.
This patch adds the header files which will be used in the subsquent
board / drivers to enable support for hi6220 hikey board.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/include/asm/arch-armv8/hi6220.h           | 324 +++++++++++++++++++
 .../include/asm/arch-armv8/hi6220_regs_alwayson.h  | 349 +++++++++++++++++++++
 2 files changed, 673 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-armv8/hi6220.h
 create mode 100644 arch/arm/include/asm/arch-armv8/hi6220_regs_alwayson.h

Patch

diff --git a/arch/arm/include/asm/arch-armv8/hi6220.h b/arch/arm/include/asm/arch-armv8/hi6220.h
new file mode 100644
index 0000000..3ddec91
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv8/hi6220.h
@@ -0,0 +1,324 @@ 
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __HI6220_H__
+#define __HI6220_H__
+
+#include "hi6220_regs_alwayson.h"
+
+#define HI6220_MMC0_BASE			0xF723D000
+#define HI6220_MMC1_BASE			0xF723E000
+
+#define HI6220_PMUSSI_BASE			0xF8000000
+
+#define HI6220_PERI_BASE			0xF7030000
+
+#define PERI_SC_PERIPH_CTRL1			(HI6220_PERI_BASE + 0x000)
+
+#define PERI_CTRL1_ETR_AXI_CSYSREQ_N			(1 << 0)
+#define PERI_CTRL1_HIFI_INT_MASK			(1 << 1)
+#define PERI_CTRL1_HIFI_ALL_INT_MASK			(1 << 2)
+#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK		(1 << 16)
+#define PERI_CTRL1_HIFI_INT_MASK_MSK			(1 << 17)
+#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK		(1 << 18)
+
+
+#define PERI_SC_PERIPH_CTRL2			(HI6220_PERI_BASE + 0x004)
+
+#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0		(1 << 0)
+#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1		(1 << 2)
+#define PERI_CTRL2_NAND_SYS_MEM_SEL			(1 << 6)
+#define PERI_CTRL2_G3D_DDRT_AXI_SEL			(1 << 7)
+#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL		(1 << 8)
+#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK		(1 << 9)
+#define PERI_CTRL2_FUNC_TEST_SOFT			(1 << 12)
+#define PERI_CTRL2_CSSYS_TS_ENABLE			(1 << 15)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA			(1 << 16)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW			(1 << 20)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS			(1 << 22)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N			(1 << 26)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N			(1 << 27)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN			(1 << 28)
+
+#define PERI_SC_PERIPH_CTRL3			(HI6220_PERI_BASE + 0x008)
+
+#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR		(1 << 0)
+#define PERI_CTRL3_HIFI_HARQMEMRMP_EN			(1 << 12)
+#define PERI_CTRL3_HARQMEM_SYS_MED_SEL			(1 << 13)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1			(1 << 14)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2			(1 << 16)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3			(1 << 18)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4			(1 << 20)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5			(1 << 22)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6			(1 << 24)
+
+#define PERI_SC_PERIPH_CTRL4			(HI6220_PERI_BASE + 0x00c)
+
+#define PERI_CTRL4_PICO_FSELV				(1 << 0)
+#define PERI_CTRL4_FPGA_EXT_PHY_SEL			(1 << 3)
+#define PERI_CTRL4_PICO_REFCLKSEL			(1 << 4)
+#define PERI_CTRL4_PICO_SIDDQ				(1 << 6)
+#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM			(1 << 7)
+#define PERI_CTRL4_PICO_OGDISABLE			(1 << 8)
+#define PERI_CTRL4_PICO_COMMONONN			(1 << 9)
+#define PERI_CTRL4_PICO_VBUSVLDEXT			(1 << 10)
+#define PERI_CTRL4_PICO_VBUSVLDEXTSEL			(1 << 11)
+#define PERI_CTRL4_PICO_VATESTENB			(1 << 12)
+#define PERI_CTRL4_PICO_SUSPENDM			(1 << 14)
+#define PERI_CTRL4_PICO_SLEEPM				(1 << 15)
+#define PERI_CTRL4_BC11_C				(1 << 16)
+#define PERI_CTRL4_BC11_B				(1 << 17)
+#define PERI_CTRL4_BC11_A				(1 << 18)
+#define PERI_CTRL4_BC11_GND				(1 << 19)
+#define PERI_CTRL4_BC11_FLOAT				(1 << 20)
+#define PERI_CTRL4_OTG_PHY_SEL				(1 << 21)
+#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE		(1 << 22)
+#define PERI_CTRL4_OTG_DM_PULLDOWN			(1 << 24)
+#define PERI_CTRL4_OTG_DP_PULLDOWN			(1 << 25)
+#define PERI_CTRL4_OTG_IDPULLUP				(1 << 26)
+#define PERI_CTRL4_OTG_DRVBUS				(1 << 27)
+#define PERI_CTRL4_OTG_SESSEND				(1 << 28)
+#define PERI_CTRL4_OTG_BVALID				(1 << 29)
+#define PERI_CTRL4_OTG_AVALID				(1 << 30)
+#define PERI_CTRL4_OTG_VBUSVALID			(1 << 31)
+
+#define PERI_SC_PERIPH_CTRL5			(HI6220_PERI_BASE + 0x010)
+
+#define PERI_CTRL5_USBOTG_RES_SEL			(1 << 3)
+#define PERI_CTRL5_PICOPHY_ACAENB			(1 << 4)
+#define PERI_CTRL5_PICOPHY_BC_MODE			(1 << 5)
+#define PERI_CTRL5_PICOPHY_CHRGSEL			(1 << 6)
+#define PERI_CTRL5_PICOPHY_VDATSRCEND			(1 << 7)
+#define PERI_CTRL5_PICOPHY_VDATDETENB			(1 << 8)
+#define PERI_CTRL5_PICOPHY_DCDENB			(1 << 9)
+#define PERI_CTRL5_PICOPHY_IDDIG			(1 << 10)
+#define PERI_CTRL5_DBG_MUX				(1 << 11)
+
+#define PERI_SC_PERIPH_CTRL6			(HI6220_PERI_BASE + 0x014)
+
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA		(1 << 0)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW		(1 << 4)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS		(1 << 6)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N		(1 << 10)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N		(1 << 11)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN		(1 << 12)
+
+#define PERI_SC_PERIPH_CTRL8			(HI6220_PERI_BASE + 0x018)
+
+#define PERI_CTRL8_PICOPHY_TXRISETUNE0			(1 << 0)
+#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0		(1 << 2)
+#define PERI_CTRL8_PICOPHY_TXRESTUNE0			(1 << 4)
+#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0			(1 << 6)
+#define PERI_CTRL8_PICOPHY_COMPDISTUNE0			(1 << 8)
+#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0		(1 << 11)
+#define PERI_CTRL8_PICOPHY_OTGTUNE0			(1 << 12)
+#define PERI_CTRL8_PICOPHY_SQRXTUNE0			(1 << 16)
+#define PERI_CTRL8_PICOPHY_TXVREFTUNE0			(1 << 20)
+#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0			(1 << 28)
+
+#define PERI_SC_PERIPH_CTRL9			(HI6220_PERI_BASE + 0x01c)
+
+#define PERI_CTRL9_PICOPLY_TESTCLKEN			(1 << 0)
+#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL		(1 << 1)
+#define PERI_CTRL9_PICOPLY_TESTADDR			(1 << 4)
+#define PERI_CTRL9_PICOPLY_TESTDATAIN			(1 << 8)
+
+#define PERI_SC_PERIPH_CTRL10			(HI6220_PERI_BASE + 0x020)
+#define PERI_SC_PERIPH_CTRL12			(HI6220_PERI_BASE + 0x024)
+#define PERI_SC_PERIPH_CTRL13			(HI6220_PERI_BASE + 0x028)
+#define PERI_SC_PERIPH_CTRL14			(HI6220_PERI_BASE + 0x02c)
+
+#define PERI_SC_DDR_CTRL0			(HI6220_PERI_BASE + 0x050)
+#define PERI_SC_PERIPH_STAT1			(HI6220_PERI_BASE + 0x094)
+
+#define PERI_SC_PERIPH_CLK0_EN			(HI6220_PERI_BASE + 0x200)
+#define PERI_SC_PERIPH_CLK0_DIS			(HI6220_PERI_BASE + 0x204)
+#define PERI_SC_PERIPH_CLK0_STAT		(HI6220_PERI_BASE + 0x208)
+
+#define PERI_CLK0_MMC0					(1 << 0)
+#define PERI_CLK0_MMC1					(1 << 1)
+#define PERI_CLK0_MMC2					(1 << 2)
+#define PERI_CLK0_NANDC					(1 << 3)
+#define PERI_CLK0_USBOTG				(1 << 4)
+#define PERI_CLK0_PICOPHY				(1 << 5)
+#define PERI_CLK0_PLL					(1 << 6)
+
+#define PERI_SC_PERIPH_CLK1_EN			(HI6220_PERI_BASE + 0x210)
+#define PERI_SC_PERIPH_CLK1_DIS			(HI6220_PERI_BASE + 0x214)
+#define PERI_SC_PERIPH_CLK1_STAT		(HI6220_PERI_BASE + 0x218)
+
+#define PERI_CLK1_HIFI					(1 << 0)
+#define PERI_CLK1_DIGACODEC				(1 << 5)
+
+
+#define PERI_SC_PERIPH_CLK2_EN			(HI6220_PERI_BASE + 0x220)
+#define PERI_SC_PERIPH_CLK2_DIS			(HI6220_PERI_BASE + 0x224)
+#define PERI_SC_PERIPH_CLK2_STAT		(HI6220_PERI_BASE + 0x228)
+
+#define PERI_CLK2_IPF					(1 << 0)
+#define PERI_CLK2_SOCP					(1 << 1)
+#define PERI_CLK2_DMAC					(1 << 2)
+#define PERI_CLK2_SECENG				(1 << 3)
+#define PERI_CLK2_HPM0					(1 << 5)
+#define PERI_CLK2_HPM1					(1 << 6)
+#define PERI_CLK2_HPM2					(1 << 7)
+#define PERI_CLK2_HPM3					(1 << 8)
+
+
+#define PERI_SC_PERIPH_CLK3_EN			(HI6220_PERI_BASE + 0x230)
+#define PERI_SC_PERIPH_CLK3_DIS			(HI6220_PERI_BASE + 0x234)
+#define PERI_SC_PERIPH_CLK3_STAT		(HI6220_PERI_BASE + 0x238)
+
+
+
+
+#define PERI_SC_PERIPH_CLK8_EN			(HI6220_PERI_BASE + 0x240)
+#define PERI_SC_PERIPH_CLK8_DIS			(HI6220_PERI_BASE + 0x244)
+#define PERI_SC_PERIPH_CLK8_STAT		(HI6220_PERI_BASE + 0x248)
+
+#define PERI_CLK8_RS0					(1 << 0)
+#define PERI_CLK8_RS2					(1 << 1)
+#define PERI_CLK8_RS3					(1 << 2)
+#define PERI_CLK8_MS0					(1 << 3)
+#define PERI_CLK8_MS2					(1 << 5)
+#define PERI_CLK8_XG2RAM0				(1 << 6)
+#define PERI_CLK8_X2SRAM				(1 << 7)
+#define PERI_CLK8_SRAM					(1 << 8)
+#define PERI_CLK8_ROM					(1 << 9)
+#define PERI_CLK8_HARQ					(1 << 10)
+#define PERI_CLK8_MMU					(1 << 11)
+#define PERI_CLK8_DDRC					(1 << 12)
+#define PERI_CLK8_DDRPHY				(1 << 13)
+#define PERI_CLK8_DDRPHY_REF				(1 << 14)
+#define PERI_CLK8_X2X_SYSNOC				(1 << 15)
+#define PERI_CLK8_X2X_CCPU				(1 << 16)
+#define PERI_CLK8_DDRT					(1 << 17)
+#define PERI_CLK8_DDRPACK_RS				(1 << 18)
+
+
+#define PERI_SC_PERIPH_CLK9_EN			(HI6220_PERI_BASE + 0x250)
+#define PERI_SC_PERIPH_CLK9_DIS			(HI6220_PERI_BASE + 0x254)
+#define PERI_SC_PERIPH_CLK9_STAT		(HI6220_PERI_BASE + 0x258)
+
+#define PERI_CLK9_CARM_DAP				(1 << 0)
+#define PERI_CLK9_CARM_ATB				(1 << 1)
+#define PERI_CLK9_CARM_LBUS				(1 << 2)
+#define PERI_CLK9_CARM_KERNEL				(1 << 3)
+
+
+#define PERI_SC_PERIPH_CLK10_EN			(HI6220_PERI_BASE + 0x260)
+#define PERI_SC_PERIPH_CLK10_DIS		(HI6220_PERI_BASE + 0x264)
+#define PERI_SC_PERIPH_CLK10_STAT		(HI6220_PERI_BASE + 0x268)
+
+#define PERI_CLK10_IPF_CCPU				(1 << 0)
+#define PERI_CLK10_SOCP_CCPU				(1 << 1)
+#define PERI_CLK10_SECENG_CCPU				(1 << 2)
+#define PERI_CLK10_HARQ_CCPU				(1 << 3)
+#define PERI_CLK10_IPF_MCU				(1 << 16)
+#define PERI_CLK10_SOCP_MCU				(1 << 17)
+#define PERI_CLK10_SECENG_MCU				(1 << 18)
+#define PERI_CLK10_HARQ_MCU				(1 << 19)
+
+#define PERI_SC_PERIPH_CLK12_EN			(HI6220_PERI_BASE + 0x270)
+#define PERI_SC_PERIPH_CLK12_DIS		(HI6220_PERI_BASE + 0x274)
+#define PERI_SC_PERIPH_CLK12_STAT		(HI6220_PERI_BASE + 0x278)
+
+#define PERI_CLK12_HIFI_SRC				(1 << 0)
+#define PERI_CLK12_MMC0_SRC				(1 << 1)
+#define PERI_CLK12_MMC1_SRC				(1 << 2)
+#define PERI_CLK12_MMC2_SRC				(1 << 3)
+#define PERI_CLK12_SYSPLL_DIV				(1 << 4)
+#define PERI_CLK12_TPIU_SRC				(1 << 5)
+#define PERI_CLK12_MMC0_HF				(1 << 6)
+#define PERI_CLK12_MMC1_HF				(1 << 7)
+#define PERI_CLK12_PLL_TEST_SRC				(1 << 8)
+#define PERI_CLK12_CODEC_SOC				(1 << 9)
+#define PERI_CLK12_MEDIA				(1 << 10)
+
+#define PERI_SC_PERIPH_RST0_EN			(HI6220_PERI_BASE + 0x300)
+#define PERI_SC_PERIPH_RST0_DIS			(HI6220_PERI_BASE + 0x304)
+#define PERI_SC_PERIPH_RST0_STAT		(HI6220_PERI_BASE + 0x308)
+
+#define PERI_RST0_MMC0					(1 << 0)
+#define PERI_RST0_MMC1					(1 << 1)
+#define PERI_RST0_MMC2					(1 << 2)
+#define PERI_RST0_NANDC					(1 << 3)
+#define PERI_RST0_USBOTG_BUS				(1 << 4)
+#define PERI_RST0_POR_PICOPHY				(1 << 5)
+#define PERI_RST0_USBOTG				(1 << 6)
+#define PERI_RST0_USBOTG_32K				(1 << 7)
+
+
+#define PERI_SC_PERIPH_RST1_EN			(HI6220_PERI_BASE + 0x310)
+#define PERI_SC_PERIPH_RST1_DIS			(HI6220_PERI_BASE + 0x314)
+#define PERI_SC_PERIPH_RST1_STAT		(HI6220_PERI_BASE + 0x318)
+
+#define PERI_RST1_HIFI					(1 << 0)
+#define PERI_RST1_DIGACODEC				(1 << 5)
+
+
+#define PERI_SC_PERIPH_RST2_EN			(HI6220_PERI_BASE + 0x320)
+#define PERI_SC_PERIPH_RST2_DIS			(HI6220_PERI_BASE + 0x324)
+#define PERI_SC_PERIPH_RST2_STAT		(HI6220_PERI_BASE + 0x328)
+
+#define PERI_RST2_IPF					(1 << 0)
+#define PERI_RST2_SOCP					(1 << 1)
+#define PERI_RST2_DMAC					(1 << 2)
+#define PERI_RST2_SECENG				(1 << 3)
+#define PERI_RST2_ABB					(1 << 4)
+#define PERI_RST2_HPM0					(1 << 5)
+#define PERI_RST2_HPM1					(1 << 6)
+#define PERI_RST2_HPM2					(1 << 7)
+#define PERI_RST2_HPM3					(1 << 8)
+
+
+#define PERI_SC_PERIPH_RST3_EN			(HI6220_PERI_BASE + 0x330)
+#define PERI_SC_PERIPH_RST3_DIS			(HI6220_PERI_BASE + 0x334)
+#define PERI_SC_PERIPH_RST3_STAT		(HI6220_PERI_BASE + 0x338)
+
+#define PERI_RST3_CSSYS					(1 << 0)
+#define PERI_RST3_I2C0					(1 << 1)
+#define PERI_RST3_I2C1					(1 << 2)
+#define PERI_RST3_I2C2					(1 << 3)
+#define PERI_RST3_I2C3					(1 << 4)
+#define PERI_RST3_UART1					(1 << 5)
+#define PERI_RST3_UART2					(1 << 6)
+#define PERI_RST3_UART3					(1 << 7)
+#define PERI_RST3_UART4					(1 << 8)
+#define PERI_RST3_SSP					(1 << 9)
+#define PERI_RST3_PWM					(1 << 10)
+#define PERI_RST3_BLPWM					(1 << 11)
+#define PERI_RST3_TSENSOR				(1 << 12)
+#define PERI_RST3_DAPB					(1 << 18)
+#define PERI_RST3_HKADC					(1 << 19)
+#define PERI_RST3_CODEC					(1 << 20)
+
+
+#define PERI_SC_PERIPH_RST8_EN			(HI6220_PERI_BASE + 0x340)
+#define PERI_SC_PERIPH_RST8_DIS			(HI6220_PERI_BASE + 0x344)
+#define PERI_SC_PERIPH_RST8_STAT		(HI6220_PERI_BASE + 0x338)
+
+#define PERI_RST8_RS0					(1 << 0)
+#define PERI_RST8_RS2					(1 << 1)
+#define PERI_RST8_RS3					(1 << 2)
+#define PERI_RST8_MS0					(1 << 3)
+#define PERI_RST8_MS2					(1 << 5)
+#define PERI_RST8_XG2RAM0				(1 << 6)
+#define PERI_RST8_X2SRAM_TZMA				(1 << 7)
+#define PERI_RST8_SRAM					(1 << 8)
+#define PERI_RST8_HARQ					(1 << 10)
+#define PERI_RST8_DDRC					(1 << 12)
+#define PERI_RST8_DDRC_APB				(1 << 13)
+#define PERI_RST8_DDRPACK_APB				(1 << 14)
+#define PERI_RST8_DDRT					(1 << 17)
+
+#define PERI_SC_CLK0_SEL			(HI6220_PERI_BASE + 0x400)
+#define PERI_SC_CLKCFG8BIT1			(HI6220_PERI_BASE + 0x494)
+#define PERI_SC_CLKCFG8BIT2			(HI6220_PERI_BASE + 0x498)
+#define PERI_SC_RESERVED8_ADDR			(HI6220_PERI_BASE + 0xd04)
+
+#endif /*__HI62220_H__*/
diff --git a/arch/arm/include/asm/arch-armv8/hi6220_regs_alwayson.h b/arch/arm/include/asm/arch-armv8/hi6220_regs_alwayson.h
new file mode 100644
index 0000000..3f0205a
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv8/hi6220_regs_alwayson.h
@@ -0,0 +1,349 @@ 
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __HI6220_ALWAYSON_H__
+#define __HI6220_ALWAYSON_H__
+
+#define ALWAYSON_CTRL_BASE			0xF7800000
+
+#define ALWAYSON_SC_SYS_CTRL0			(ALWAYSON_CTRL_BASE + 0x000)
+
+#define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL			0x004
+#define ALWAYSON_SC_SYS_CTRL0_MODE_MASK				0x007
+
+#define ALWAYSON_SC_SYS_CTRL1			(ALWAYSON_CTRL_BASE + 0x004)
+
+#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG			(1 << 0)
+#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM			(1 << 1)
+#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP			(1 << 2)
+#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL			(1 << 3)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG		(1 << 4)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG		(1 << 6)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG			(1 << 7)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG		(1 << 8)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG			(1 << 9)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG		(1 << 10)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1		(1 << 11)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT			(1 << 12)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT			(1 << 13)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG			(1 << 15)
+#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK		(1 << 16)
+#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK		(1 << 17)
+#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK			(1 << 18)
+#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK			(1 << 19)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK		(1 << 20)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK	(1 << 22)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK		(1 << 23)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK	(1 << 24)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK		(1 << 25)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK		(1 << 26)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK		(1 << 27)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK		(1 << 28)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK		(1 << 29)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK		(1 << 31)
+
+#define ALWAYSON_SC_SYS_CTRL2			(ALWAYSON_CTRL_BASE + 0x008)
+
+#define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR		(1 << 26)
+#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR		(1 << 27)
+#define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR		(1 << 28)
+#define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR		(1 << 29)
+#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR		(1 << 30)
+#define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR		(1 << 31)
+
+#define ALWAYSON_SC_SYS_STAT0			(ALWAYSON_CTRL_BASE + 0x010)
+
+#define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT			(1 << 25)
+#define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT			(1 << 26)
+#define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT			(1 << 27)
+#define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT		(1 << 28)
+#define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT		(1 << 29)
+#define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT			(1 << 30)
+#define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT			(1 << 31)
+
+#define ALWAYSON_SC_SYS_STAT1			(ALWAYSON_CTRL_BASE + 0x014)
+
+#define ALWAYSON_SC_SYS_STAT1_MODE_STATUS			(1 << 0)
+#define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK			(1 << 16)
+#define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK			(1 << 17)
+#define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK			(1 << 19)
+#define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT			(1 << 20)
+#define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG			(1 << 27)
+#define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK		(1 << 28)
+#define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE		(1 << 29)
+
+#define ALWAYSON_SC_MCU_IMCTRL			(ALWAYSON_CTRL_BASE + 0x018)
+#define ALWAYSON_SC_MCU_IMSTAT			(ALWAYSON_CTRL_BASE + 0x01C)
+#define ALWAYSON_SC_SECONDRY_INT_EN0		(ALWAYSON_CTRL_BASE + 0x044)
+#define ALWAYSON_SC_SECONDRY_INT_STATR0		(ALWAYSON_CTRL_BASE + 0x048)
+#define ALWAYSON_SC_SECONDRY_INT_STATM0		(ALWAYSON_CTRL_BASE + 0x04C)
+#define ALWAYSON_SC_MCU_WKUP_INT_EN6		(ALWAYSON_CTRL_BASE + 0x054)
+#define ALWAYSON_SC_MCU_WKUP_INT_STATR6		(ALWAYSON_CTRL_BASE + 0x058)
+#define ALWAYSON_SC_MCU_WKUP_INT_STATM6		(ALWAYSON_CTRL_BASE + 0x05C)
+#define ALWAYSON_SC_MCU_WKUP_INT_EN5		(ALWAYSON_CTRL_BASE + 0x064)
+#define ALWAYSON_SC_MCU_WKUP_INT_STATR5		(ALWAYSON_CTRL_BASE + 0x068)
+#define ALWAYSON_SC_MCU_WKUP_INT_STATM5		(ALWAYSON_CTRL_BASE + 0x06C)
+#define ALWAYSON_SC_MCU_WKUP_INT_EN4		(ALWAYSON_CTRL_BASE + 0x094)
+#define ALWAYSON_SC_MCU_WKUP_INT_STATR4		(ALWAYSON_CTRL_BASE + 0x098)
+#define ALWAYSON_SC_MCU_WKUP_INT_STATM4		(ALWAYSON_CTRL_BASE + 0x09C)
+#define ALWAYSON_SC_MCU_WKUP_INT_EN0		(ALWAYSON_CTRL_BASE + 0x0A8)
+#define ALWAYSON_SC_MCU_WKUP_INT_STATR0		(ALWAYSON_CTRL_BASE + 0x0AC)
+#define ALWAYSON_SC_MCU_WKUP_INT_STATM0		(ALWAYSON_CTRL_BASE + 0x0B0)
+#define ALWAYSON_SC_MCU_WKUP_INT_EN1		(ALWAYSON_CTRL_BASE + 0x0B4)
+#define ALWAYSON_SC_MCU_WKUP_INT_STATR1		(ALWAYSON_CTRL_BASE + 0x0B8)
+#define ALWAYSON_SC_MCU_WKUP_INT_STATM1		(ALWAYSON_CTRL_BASE + 0x0BC)
+#define ALWAYSON_SC_INT_STATR			(ALWAYSON_CTRL_BASE + 0x0C4)
+#define ALWAYSON_SC_INT_STATM			(ALWAYSON_CTRL_BASE + 0x0C8)
+#define ALWAYSON_SC_INT_CLEAR			(ALWAYSON_CTRL_BASE + 0x0CC)
+#define ALWAYSON_SC_INT_EN_SET			(ALWAYSON_CTRL_BASE + 0x0D0)
+#define ALWAYSON_SC_INT_EN_DIS			(ALWAYSON_CTRL_BASE + 0x0D4)
+#define ALWAYSON_SC_INT_EN_STAT			(ALWAYSON_CTRL_BASE + 0x0D8)
+#define ALWAYSON_SC_INT_STATR1			(ALWAYSON_CTRL_BASE + 0x0E4)
+#define ALWAYSON_SC_INT_STATM1			(ALWAYSON_CTRL_BASE + 0x0E8)
+#define ALWAYSON_SC_INT_CLEAR1			(ALWAYSON_CTRL_BASE + 0x0EC)
+#define ALWAYSON_SC_INT_EN_SET1			(ALWAYSON_CTRL_BASE + 0x0F0)
+#define ALWAYSON_SC_INT_EN_DIS1			(ALWAYSON_CTRL_BASE + 0x0F4)
+#define ALWAYSON_SC_INT_EN_STAT1		(ALWAYSON_CTRL_BASE + 0x0F8)
+#define ALWAYSON_SC_TIMER_EN0			(ALWAYSON_CTRL_BASE + 0x1D0)
+#define ALWAYSON_SC_TIMER_EN1			(ALWAYSON_CTRL_BASE + 0x1D4)
+#define ALWAYSON_SC_TIMER_EN4			(ALWAYSON_CTRL_BASE + 0x1F0)
+#define ALWAYSON_SC_TIMER_EN5			(ALWAYSON_CTRL_BASE + 0x1F4)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL0		(ALWAYSON_CTRL_BASE + 0x400)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL1		(ALWAYSON_CTRL_BASE + 0x404)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL2		(ALWAYSON_CTRL_BASE + 0x408)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3		(ALWAYSON_CTRL_BASE + 0x40C)
+
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3			0x003
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK			0x007
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT		(1 << 3)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG		(1 << 4)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1		(1 << 8)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0		(1 << 9)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD		(1 << 10)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED	(1 << 11)
+
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL4		(ALWAYSON_CTRL_BASE + 0x410)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL5		(ALWAYSON_CTRL_BASE + 0x414)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL6		(ALWAYSON_CTRL_BASE + 0x418)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL7		(ALWAYSON_CTRL_BASE + 0x41C)
+#define ALWAYSON_SC_MCU_SUBSYS_STAT0		(ALWAYSON_CTRL_BASE + 0x440)
+#define ALWAYSON_SC_MCU_SUBSYS_STAT1		(ALWAYSON_CTRL_BASE + 0x444)
+#define ALWAYSON_SC_MCU_SUBSYS_STAT2		(ALWAYSON_CTRL_BASE + 0x448)
+#define ALWAYSON_SC_MCU_SUBSYS_STAT3		(ALWAYSON_CTRL_BASE + 0x44C)
+#define ALWAYSON_SC_MCU_SUBSYS_STAT4		(ALWAYSON_CTRL_BASE + 0x450)
+#define ALWAYSON_SC_MCU_SUBSYS_STAT5		(ALWAYSON_CTRL_BASE + 0x454)
+#define ALWAYSON_SC_MCU_SUBSYS_STAT6		(ALWAYSON_CTRL_BASE + 0x458)
+#define ALWAYSON_SC_MCU_SUBSYS_STAT7		(ALWAYSON_CTRL_BASE + 0x45C)
+
+#define ALWAYSON_SC_PERIPH_CLK4_EN		(ALWAYSON_CTRL_BASE + 0x630)
+
+#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU			(1 << 0)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP			(1 << 3)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0		(1 << 4)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1		(1 << 5)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0		(1 << 6)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1		(1 << 7)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S			(1 << 8)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS			(1 << 9)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC			(1 << 10)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC			(1 << 11)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0			(1 << 12)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1			(1 << 13)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2			(1 << 14)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0			(1 << 15)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1			(1 << 16)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2			(1 << 17)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3			(1 << 18)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4			(1 << 19)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5			(1 << 20)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6			(1 << 21)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7			(1 << 22)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8			(1 << 23)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0			(1 << 24)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0			(1 << 25)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1			(1 << 26)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI			(1 << 27)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH		(1 << 28)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON		(1 << 29)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM			(1 << 30)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD			(1 << 31)
+
+#define ALWAYSON_SC_PERIPH_CLK4_DIS		(ALWAYSON_CTRL_BASE + 0x634)
+#define ALWAYSON_SC_PERIPH_CLK4_STAT		(ALWAYSON_CTRL_BASE + 0x638)
+
+#define ALWAYSON_SC_PERIPH_CLK5_EN		(ALWAYSON_CTRL_BASE + 0x63C)
+
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU		(1 << 0)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU		(1 << 1)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU		(1 << 2)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU		(1 << 3)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU		(1 << 16)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU		(1 << 17)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU			(1 << 18)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU		(1 << 19)
+
+#define ALWAYSON_SC_PERIPH_CLK5_DIS		(ALWAYSON_CTRL_BASE + 0x640)
+#define ALWAYSON_SC_PERIPH_CLK5_STAT		(ALWAYSON_CTRL_BASE + 0x644)
+
+#define ALWAYSON_SC_PERIPH_RST4_EN		(ALWAYSON_CTRL_BASE + 0x6F0)
+#define ALWAYSON_SC_PERIPH_RST4_DIS		(ALWAYSON_CTRL_BASE + 0x6F4)
+
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N		(1 << 0)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N		(1 << 1)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N		(1 << 2)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N		(1 << 3)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N		(1 << 4)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N		(1 << 5)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N		(1 << 6)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N		(1 << 7)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N		(1 << 8)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N		(1 << 9)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N		(1 << 10)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N		(1 << 12)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N		(1 << 13)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N		(1 << 14)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N		(1 << 15)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N		(1 << 16)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N		(1 << 17)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N		(1 << 18)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N		(1 << 19)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N		(1 << 20)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N		(1 << 21)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N		(1 << 22)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N		(1 << 23)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N		(1 << 24)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N		(1 << 25)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N		(1 << 26)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N		(1 << 27)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N		(1 << 28)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N		(1 << 29)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB		(1 << 30)
+
+#define ALWAYSON_SC_PERIPH_RST4_STAT		(ALWAYSON_CTRL_BASE + 0x6F8)
+
+#define ALWAYSON_SC_PERIPH_RST5_EN		(ALWAYSON_CTRL_BASE + 0x6FC)
+#define ALWAYSON_SC_PERIPH_RST5_DIS		(ALWAYSON_CTRL_BASE + 0x700)
+#define ALWAYSON_SC_PERIPH_RST5_STAT		(ALWAYSON_CTRL_BASE + 0x704)
+
+#define ALWAYSON_SC_PW_CLK0_EN			(ALWAYSON_CTRL_BASE + 0x800)
+#define ALWAYSON_SC_PW_CLK0_DIS			(ALWAYSON_CTRL_BASE + 0x804)
+#define ALWAYSON_SC_PW_CLK0_STAT		(ALWAYSON_CTRL_BASE + 0x808)
+
+#define ALWAYSON_SC_PW_RST0_EN			(ALWAYSON_CTRL_BASE + 0x810)
+#define ALWAYSON_SC_PW_RST0_DIS			(ALWAYSON_CTRL_BASE + 0x814)
+#define ALWAYSON_SC_PW_RST0_STAT0		(ALWAYSON_CTRL_BASE + 0x818)
+
+#define ALWAYSON_SC_PW_ISOEN0			(ALWAYSON_CTRL_BASE + 0x820)
+#define ALWAYSON_SC_PW_ISODIS0			(ALWAYSON_CTRL_BASE + 0x824)
+#define ALWAYSON_SC_PW_ISO_STAT0		(ALWAYSON_CTRL_BASE + 0x828)
+#define ALWAYSON_SC_PW_MTCMOS_EN0		(ALWAYSON_CTRL_BASE + 0x830)
+#define ALWAYSON_SC_PW_MTCMOS_DIS0		(ALWAYSON_CTRL_BASE + 0x834)
+#define ALWAYSON_SC_PW_MTCMOS_STAT0		(ALWAYSON_CTRL_BASE + 0x838)
+#define ALWAYSON_SC_PW_MTCMOS_ACK_STAT0		(ALWAYSON_CTRL_BASE + 0x83C)
+#define ALWAYSON_SC_PW_MTCMOS_TIMEOUT_STAT0	(ALWAYSON_CTRL_BASE + 0x840)
+#define ALWAYSON_SC_PW_STAT0			(ALWAYSON_CTRL_BASE + 0x850)
+#define ALWAYSON_SC_PW_STAT1			(ALWAYSON_CTRL_BASE + 0x854)
+#define ALWAYSON_SC_SYSTEST_STAT		(ALWAYSON_CTRL_BASE + 0x880)
+#define ALWAYSON_SC_SYSTEST_SLICER_CNT0		(ALWAYSON_CTRL_BASE + 0x890)
+#define ALWAYSON_SC_SYSTEST_SLICER_CNT1		(ALWAYSON_CTRL_BASE + 0x894)
+#define ALWAYSON_SC_PW_CTRL1			(ALWAYSON_CTRL_BASE + 0x8C8)
+#define ALWAYSON_SC_PW_CTRL			(ALWAYSON_CTRL_BASE + 0x8CC)
+#define ALWAYSON_SC_MCPU_VOTEEN			(ALWAYSON_CTRL_BASE + 0x8D0)
+#define ALWAYSON_SC_MCPU_VOTEDIS		(ALWAYSON_CTRL_BASE + 0x8D4)
+#define ALWAYSON_SC_MCPU_VOTESTAT		(ALWAYSON_CTRL_BASE + 0x8D8)
+#define ALWAYSON_SC_MCPU_VOTE_MSK0		(ALWAYSON_CTRL_BASE + 0x8E0)
+#define ALWAYSON_SC_MCPU_VOTE_MSK1		(ALWAYSON_CTRL_BASE + 0x8E4)
+#define ALWAYSON_SC_MCPU_VOTESTAT0_MSK		(ALWAYSON_CTRL_BASE + 0x8E8)
+#define ALWAYSON_SC_MCPU_VOTESTAT1_MSK		(ALWAYSON_CTRL_BASE + 0x8EC)
+#define ALWAYSON_SC_PERI_VOTEEN			(ALWAYSON_CTRL_BASE + 0x8F0)
+#define ALWAYSON_SC_PERI_VOTEDIS		(ALWAYSON_CTRL_BASE + 0x8F4)
+#define ALWAYSON_SC_PERI_VOTESTAT		(ALWAYSON_CTRL_BASE + 0x8F8)
+#define ALWAYSON_SC_PERI_VOTE_MSK0		(ALWAYSON_CTRL_BASE + 0x900)
+#define ALWAYSON_SC_PERI_VOTE_MSK1		(ALWAYSON_CTRL_BASE + 0x904)
+#define ALWAYSON_SC_PERI_VOTESTAT0_MSK		(ALWAYSON_CTRL_BASE + 0x908)
+#define ALWAYSON_SC_PERI_VOTESTAT1_MSK		(ALWAYSON_CTRL_BASE + 0x90C)
+#define ALWAYSON_SC_ACPU_VOTEEN			(ALWAYSON_CTRL_BASE + 0x910)
+#define ALWAYSON_SC_ACPU_VOTEDIS		(ALWAYSON_CTRL_BASE + 0x914)
+#define ALWAYSON_SC_ACPU_VOTESTAT		(ALWAYSON_CTRL_BASE + 0x918)
+#define ALWAYSON_SC_ACPU_VOTE_MSK0		(ALWAYSON_CTRL_BASE + 0x920)
+#define ALWAYSON_SC_ACPU_VOTE_MSK1		(ALWAYSON_CTRL_BASE + 0x924)
+#define ALWAYSON_SC_ACPU_VOTESTAT0_MSK		(ALWAYSON_CTRL_BASE + 0x928)
+#define ALWAYSON_SC_ACPU_VOTESTAT1_MSK		(ALWAYSON_CTRL_BASE + 0x92C)
+#define ALWAYSON_SC_MCU_VOTEEN			(ALWAYSON_CTRL_BASE + 0x930)
+#define ALWAYSON_SC_MCU_VOTEDIS			(ALWAYSON_CTRL_BASE + 0x934)
+#define ALWAYSON_SC_MCU_VOTESTAT		(ALWAYSON_CTRL_BASE + 0x938)
+#define ALWAYSON_SC_MCU_VOTE_MSK0		(ALWAYSON_CTRL_BASE + 0x940)
+#define ALWAYSON_SC_MCU_VOTE_MSK1		(ALWAYSON_CTRL_BASE + 0x944)
+#define ALWAYSON_SC_MCU_VOTESTAT0_MSK		(ALWAYSON_CTRL_BASE + 0x948)
+#define ALWAYSON_SC_MCU_VOTESTAT1_MSK		(ALWAYSON_CTRL_BASE + 0x94C)
+#define ALWAYSON_SC_MCU_VOTE1EN			(ALWAYSON_CTRL_BASE + 0x960)
+#define ALWAYSON_SC_MCU_VOTE1DIS		(ALWAYSON_CTRL_BASE + 0x964)
+#define ALWAYSON_SC_MCU_VOTE1STAT		(ALWAYSON_CTRL_BASE + 0x968)
+#define ALWAYSON_SC_MCU_VOTE1_MSK0		(ALWAYSON_CTRL_BASE + 0x970)
+#define ALWAYSON_SC_MCU_VOTE1_MSK1		(ALWAYSON_CTRL_BASE + 0x974)
+#define ALWAYSON_SC_MCU_VOTE1STAT0_MSK		(ALWAYSON_CTRL_BASE + 0x978)
+#define ALWAYSON_SC_MCU_VOTE1STAT1_MSK		(ALWAYSON_CTRL_BASE + 0x97C)
+#define ALWAYSON_SC_MCU_VOTE2EN			(ALWAYSON_CTRL_BASE + 0x980)
+#define ALWAYSON_SC_MCU_VOTE2DIS		(ALWAYSON_CTRL_BASE + 0x984)
+#define ALWAYSON_SC_MCU_VOTE2STAT		(ALWAYSON_CTRL_BASE + 0x988)
+#define ALWAYSON_SC_MCU_VOTE2_MSK0		(ALWAYSON_CTRL_BASE + 0x990)
+#define ALWAYSON_SC_MCU_VOTE2_MSK1		(ALWAYSON_CTRL_BASE + 0x994)
+#define ALWAYSON_SC_MCU_VOTE2STAT0_MSK		(ALWAYSON_CTRL_BASE + 0x998)
+#define ALWAYSON_SC_MCU_VOTE2STAT1_MSK		(ALWAYSON_CTRL_BASE + 0x99C)
+#define ALWAYSON_SC_VOTE_CTRL			(ALWAYSON_CTRL_BASE + 0x9A0)
+#define ALWAYSON_SC_VOTE_STAT			(ALWAYSON_CTRL_BASE + 0x9A4)
+#define ALWAYSON_SC_ECONUM			(ALWAYSON_CTRL_BASE + 0xF00)
+#define ALWAYSON_SCCHIPID			(ALWAYSON_CTRL_BASE + 0xF10)
+#define ALWAYSON_SCSOCID			(ALWAYSON_CTRL_BASE + 0xF1C)
+#define ALWAYSON_SC_SOC_FPGA_RTL_DEF		(ALWAYSON_CTRL_BASE + 0xFE0)
+#define ALWAYSON_SC_SOC_FPGA_PR_DEF		(ALWAYSON_CTRL_BASE + 0xFE4)
+#define ALWAYSON_SC_SOC_FPGA_RES_DEF0		(ALWAYSON_CTRL_BASE + 0xFE8)
+#define ALWAYSON_SC_SOC_FPGA_RES_DEF1		(ALWAYSON_CTRL_BASE + 0xFEC)
+#define ALWAYSON_SC_XTAL_CTRL0			(ALWAYSON_CTRL_BASE + 0x102)
+#define ALWAYSON_SC_XTAL_CTRL1			(ALWAYSON_CTRL_BASE + 0x102)
+#define ALWAYSON_SC_XTAL_CTRL3			(ALWAYSON_CTRL_BASE + 0x103)
+#define ALWAYSON_SC_XTAL_CTRL5			(ALWAYSON_CTRL_BASE + 0x103)
+#define ALWAYSON_SC_XTAL_STAT0			(ALWAYSON_CTRL_BASE + 0x106)
+#define ALWAYSON_SC_XTAL_STAT1			(ALWAYSON_CTRL_BASE + 0x107)
+#define ALWAYSON_SC_EFUSE_CHIPID0		(ALWAYSON_CTRL_BASE + 0x108)
+#define ALWAYSON_SC_EFUSE_CHIPID1		(ALWAYSON_CTRL_BASE + 0x108)
+#define ALWAYSON_SC_EFUSE_SYS_CTRL		(ALWAYSON_CTRL_BASE + 0x108)
+#define ALWAYSON_SC_DEBUG_CTRL1			(ALWAYSON_CTRL_BASE + 0x128)
+#define ALWAYSON_SC_DBG_STAT			(ALWAYSON_CTRL_BASE + 0x12B)
+#define ALWAYSON_SC_ARM_DBG_KEY0		(ALWAYSON_CTRL_BASE + 0x12B)
+#define ALWAYSON_SC_RESERVED31			(ALWAYSON_CTRL_BASE + 0x13A)
+#define ALWAYSON_SC_RESERVED32			(ALWAYSON_CTRL_BASE + 0x13A)
+#define ALWAYSON_SC_RESERVED33			(ALWAYSON_CTRL_BASE + 0x13A)
+#define ALWAYSON_SC_RESERVED34			(ALWAYSON_CTRL_BASE + 0x13A)
+#define ALWAYSON_SC_RESERVED35			(ALWAYSON_CTRL_BASE + 0x13B)
+#define ALWAYSON_SC_RESERVED36			(ALWAYSON_CTRL_BASE + 0x13B)
+#define ALWAYSON_SC_RESERVED37			(ALWAYSON_CTRL_BASE + 0x13B)
+#define ALWAYSON_SC_RESERVED38			(ALWAYSON_CTRL_BASE + 0x13B)
+#define ALWAYSON_SC_ALWAYSON_SYS_CTRL0		(ALWAYSON_CTRL_BASE + 0x148)
+#define ALWAYSON_SC_ALWAYSON_SYS_CTRL1		(ALWAYSON_CTRL_BASE + 0x148)
+#define ALWAYSON_SC_ALWAYSON_SYS_CTRL2		(ALWAYSON_CTRL_BASE + 0x148)
+#define ALWAYSON_SC_ALWAYSON_SYS_CTRL3		(ALWAYSON_CTRL_BASE + 0x148)
+#define ALWAYSON_SC_ALWAYSON_SYS_CTRL10		(ALWAYSON_CTRL_BASE + 0x14A)
+#define ALWAYSON_SC_ALWAYSON_SYS_CTRL11		(ALWAYSON_CTRL_BASE + 0x14A)
+#define ALWAYSON_SC_ALWAYSON_SYS_STAT0		(ALWAYSON_CTRL_BASE + 0x14C)
+#define ALWAYSON_SC_ALWAYSON_SYS_STAT1		(ALWAYSON_CTRL_BASE + 0x14C)
+#define ALWAYSON_SC_ALWAYSON_SYS_STAT2		(ALWAYSON_CTRL_BASE + 0x14C)
+#define ALWAYSON_SC_ALWAYSON_SYS_STAT3		(ALWAYSON_CTRL_BASE + 0x14C)
+#define ALWAYSON_SC_PWUP_TIME0			(ALWAYSON_CTRL_BASE + 0x188)
+#define ALWAYSON_SC_PWUP_TIME1			(ALWAYSON_CTRL_BASE + 0x188)
+#define ALWAYSON_SC_PWUP_TIME2			(ALWAYSON_CTRL_BASE + 0x188)
+#define ALWAYSON_SC_PWUP_TIME3			(ALWAYSON_CTRL_BASE + 0x188)
+#define ALWAYSON_SC_PWUP_TIME4			(ALWAYSON_CTRL_BASE + 0x189)
+#define ALWAYSON_SC_PWUP_TIME5			(ALWAYSON_CTRL_BASE + 0x189)
+#define ALWAYSON_SC_PWUP_TIME6			(ALWAYSON_CTRL_BASE + 0x189)
+#define ALWAYSON_SC_PWUP_TIME7			(ALWAYSON_CTRL_BASE + 0x189)
+#define ALWAYSON_SC_SECURITY_CTRL1		(ALWAYSON_CTRL_BASE + 0x1C0)
+
+#define PCLK_TIMER1						(1 << 16)
+#define PCLK_TIMER0						(1 << 15)
+
+#endif /* __HI6220_ALWAYSON_H__ */