diff mbox series

[v3,3/4] arm64: dts: rockchip: Add GPU node for rk3568

Message ID 20210805025948.10900-4-ezequiel@collabora.com
State New
Headers show
Series RK3568 GPU | expand

Commit Message

Ezequiel Garcia Aug. 5, 2021, 2:59 a.m. UTC
Rockchip SoCs RK3566 and RK3568 have a Mali Gondul core
which is based on the Bifrost architecture. It has
one shader core and two execution engines.

Quoting the datasheet:

Mali-G52 1-Core-2EE
* Support 1600Mpix/s fill rate when 800MHz clock frequency
* Support 38.4GLOPs when 800MHz clock frequency

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

Comments

Johan Jonker Aug. 20, 2021, 3:08 p.m. UTC | #1
Hi Ezequiel,

Some more comments. Have a look if it is useful.

On 8/5/21 4:59 AM, Ezequiel Garcia wrote:
> Rockchip SoCs RK3566 and RK3568 have a Mali Gondul core

> which is based on the Bifrost architecture. It has

> one shader core and two execution engines.

> 

> Quoting the datasheet:

> 

> Mali-G52 1-Core-2EE

> * Support 1600Mpix/s fill rate when 800MHz clock frequency

> * Support 38.4GLOPs when 800MHz clock frequency

> 

> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

> ---

>  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++

>  1 file changed, 50 insertions(+)

> 

> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi

> index bef747fb1fe2..f8173ba63be0 100644

> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi

> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi

> @@ -121,6 +121,40 @@ opp-1800000000 {

>  		};

>  	};

>  


> +	gpu_opp_table: gpu-opp-table {


	gpu_opp_table: opp-table-1 {

Excuse for the inconvenience, but rob+dt just made a patch for opp last
month...
See opp-v2-base.yaml:
'^opp-table(-[a-z0-9]+)?$'

[PATCH v3 3/3] dt-bindings: opp: Convert to DT schema
https://lore.kernel.org/lkml/20210720144121.66713-3-robh@kernel.org/

===
A look in the manufacturer tree we can expect one more opp table in the
number sequence.
	npu_opp_table: opp-table-2 {}
https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi


> +		compatible = "operating-points-v2";

> +

> +		opp-200000000 {

> +			opp-hz = /bits/ 64 <200000000>;

> +			opp-microvolt = <825000>;

> +		};

> +

> +		opp-300000000 {

> +			opp-hz = /bits/ 64 <300000000>;

> +			opp-microvolt = <825000>;

> +		};

> +

> +		opp-400000000 {

> +			opp-hz = /bits/ 64 <400000000>;

> +			opp-microvolt = <825000>;

> +		};

> +

> +		opp-600000000 {

> +			opp-hz = /bits/ 64 <600000000>;

> +			opp-microvolt = <825000>;

> +		};

> +

> +		opp-700000000 {

> +			opp-hz = /bits/ 64 <700000000>;

> +			opp-microvolt = <900000>;

> +		};

> +

> +		opp-800000000 {

> +			opp-hz = /bits/ 64 <800000000>;

> +			opp-microvolt = <1000000>;

> +		};

> +	};

> +

>  	firmware {

>  		scmi: scmi {

>  			compatible = "arm,scmi-smc";

> @@ -332,6 +366,22 @@ power-domain@RK3568_PD_RKVENC {

>  		};

>  	};

>  

> +	gpu: gpu@fde60000 {

> +		compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";

> +		reg = <0x0 0xfde60000 0x0 0x4000>;


> +


Maybe remove this empty line as well?

> +		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

> +			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

> +			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;

> +		interrupt-names = "job", "mmu", "gpu";

> +		clocks = <&scmi_clk 1>, <&cru CLK_GPU>;

> +		clock-names = "core", "bus";

> +		operating-points-v2 = <&gpu_opp_table>;


> +		#cooling-cells = <2>;


Not a big issue, but things with "#" are only needed for dt
interpretation (not a real property). I try to drop them as far down the
list when not sort alphabetically or connected to a real property.

> +		power-domains = <&power RK3568_PD_GPU>;


> +		status = "disabled";

> +	};

> +

>  	sdmmc2: mmc@fe000000 {

>  		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";

>  		reg = <0x0 0xfe000000 0x0 0x4000>;

>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index bef747fb1fe2..f8173ba63be0 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -121,6 +121,40 @@  opp-1800000000 {
 		};
 	};
 
+	gpu_opp_table: gpu-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <900000>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1000000>;
+		};
+	};
+
 	firmware {
 		scmi: scmi {
 			compatible = "arm,scmi-smc";
@@ -332,6 +366,22 @@  power-domain@RK3568_PD_RKVENC {
 		};
 	};
 
+	gpu: gpu@fde60000 {
+		compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
+		reg = <0x0 0xfde60000 0x0 0x4000>;
+
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "job", "mmu", "gpu";
+		clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
+		clock-names = "core", "bus";
+		operating-points-v2 = <&gpu_opp_table>;
+		#cooling-cells = <2>;
+		power-domains = <&power RK3568_PD_GPU>;
+		status = "disabled";
+	};
+
 	sdmmc2: mmc@fe000000 {
 		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xfe000000 0x0 0x4000>;