@@ -42,6 +42,48 @@ properties:
"#reset-cells":
const: 1
+ tegra-clocks:
+ description: child nodes are the output clocks from the CAR
+ type: object
+
+ patternProperties:
+ "^[a-z]+[0-9]+$":
+ type: object
+ properties:
+ compatible:
+ allOf:
+ - items:
+ - enum:
+ - nvidia,tegra20-sclk
+ - nvidia,tegra30-sclk
+ - nvidia,tegra30-pllc
+ - nvidia,tegra30-plle
+ - nvidia,tegra30-pllm
+ - const: nvidia,tegra-clock
+
+ operating-points-v2:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to OPP table that contains frequencies, voltages and
+ opp-supported-hw property, which is a bitfield indicating
+ SoC process or speedo ID mask.
+
+ clocks:
+ items:
+ - description: node's clock
+
+ power-domains:
+ maxItems: 1
+ description: phandle to the core SoC power domain
+
+ required:
+ - compatible
+ - operating-points-v2
+ - clocks
+ - power-domains
+
+ additionalProperties: false
+
required:
- compatible
- reg
@@ -59,6 +101,15 @@ examples:
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ tegra-clocks {
+ sclk {
+ compatible = "nvidia,tegra20-sclk", "nvidia,tegra-clock";
+ operating-points-v2 = <&opp_table>;
+ clocks = <&tegra_car TEGRA20_CLK_SCLK>;
+ power-domains = <&domain>;
+ };
+ };
};
usb-controller@c5004000 {
Document tegra-clocks sub-node which describes Tegra SoC clocks that require a higher voltage of the core power domain in order to operate properly on a higher clock rates. Each node contains a phandle to OPP table and power domain. The root PLLs and system clocks don't have any specific device dedicated to them, clock controller is in charge of managing power for them. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../bindings/clock/nvidia,tegra20-car.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+)