| Message ID | 1629445443-10300-3-git-send-email-haibo.chen@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/4] spi: spi-nxp-fspi: enable runtime pm for fspi | expand |
Hi Haibo, > -----Original Message----- > From: haibo.chen@nxp.com <haibo.chen@nxp.com> > Sent: Friday, August 20, 2021 1:14 PM > To: Ashish Kumar <ashish.kumar@nxp.com>; yogeshgaur.83@gmail.com; > broonie@kernel.org > Cc: linux-spi@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>; Bough Chen > <haibo.chen@nxp.com> > Subject: [EXT] [PATCH 3/4] spi: spi-nxp-fspi: add DDR mode support > > Caution: EXT Email > > From: Haibo Chen <haibo.chen@nxp.com> > > For LUT, add DDR command support. > Also use new API spi_mem_dtr_supports_op() to check the DTR mode. > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Thanks for submitting patch to support octal DTR. > --- > drivers/spi/spi-nxp-fspi.c | 25 ++++++++++++++++++++----- > 1 file changed, 20 insertions(+), 5 deletions(-) > > diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index > a764eb475aed..f7acad2cbe64 100644 > --- a/drivers/spi/spi-nxp-fspi.c > +++ b/drivers/spi/spi-nxp-fspi.c > @@ -486,6 +486,9 @@ static bool nxp_fspi_supports_op(struct spi_mem > *mem, > op->data.nbytes > f->devtype_data->txfifo) > return false; > > + if (op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr) > + return spi_mem_dtr_supports_op(mem, op); > + [snip] Now that spi-nor framework and flexspi driver supports octal DTR, if device-tree specifies RX and TX bus-width as <8,8> , then above change will always make sure to select DTR mode and SDR will never get selected. Please note, Layerscape LX2160A and LX2162A are two platforms which have micron mt35xu512aba (support octal dtr) and are causing probe failure with these patches as required dependencies for enabling DTR are not met. Since framework selects maximum supported capability, I think there should be a mechanism to choose SDR or DTR mode in driver itself. This will also help for a platform to fallback from DTR to SDR in case DTR doesn't work. We can enable this feature as a quirk or by reading a property from device-tree. Please let me know your views. Regards Kuldeep
> -----Original Message----- > From: Kuldeep Singh > Sent: 2021年8月31日 18:42 > To: Bough Chen <haibo.chen@nxp.com> > Cc: linux-spi@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>; Bough Chen > <haibo.chen@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>; > broonie@kernel.org > Subject: RE: [EXT] [PATCH 3/4] spi: spi-nxp-fspi: add DDR mode support > > Hi Haibo, > > > -----Original Message----- > > From: haibo.chen@nxp.com <haibo.chen@nxp.com> > > Sent: Friday, August 20, 2021 1:14 PM > > To: Ashish Kumar <ashish.kumar@nxp.com>; yogeshgaur.83@gmail.com; > > broonie@kernel.org > > Cc: linux-spi@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>; Bough > > Chen <haibo.chen@nxp.com> > > Subject: [EXT] [PATCH 3/4] spi: spi-nxp-fspi: add DDR mode support > > > > Caution: EXT Email > > > > From: Haibo Chen <haibo.chen@nxp.com> > > > > For LUT, add DDR command support. > > Also use new API spi_mem_dtr_supports_op() to check the DTR mode. > > > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> > > Thanks for submitting patch to support octal DTR. > > > --- > > drivers/spi/spi-nxp-fspi.c | 25 ++++++++++++++++++++----- > > 1 file changed, 20 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c > > index > > a764eb475aed..f7acad2cbe64 100644 > > --- a/drivers/spi/spi-nxp-fspi.c > > +++ b/drivers/spi/spi-nxp-fspi.c > > @@ -486,6 +486,9 @@ static bool nxp_fspi_supports_op(struct spi_mem > > *mem, > > op->data.nbytes > f->devtype_data->txfifo) > > return false; > > > > + if (op->cmd.dtr && op->addr.dtr && op->dummy.dtr && > op->data.dtr) > > + return spi_mem_dtr_supports_op(mem, op); > > + > [snip] > > Now that spi-nor framework and flexspi driver supports octal DTR, if > device-tree specifies RX and TX bus-width as <8,8> , then above change will > always make sure to select DTR mode and SDR will never get selected. > Please note, Layerscape LX2160A and LX2162A are two platforms which have > micron mt35xu512aba (support octal dtr) and are causing probe failure with > these patches as required dependencies for enabling DTR are not met. > > Since framework selects maximum supported capability, I think there should be > a mechanism to choose SDR or DTR mode in driver itself. > This will also help for a platform to fallback from DTR to SDR in case DTR > doesn't work. > We can enable this feature as a quirk or by reading a property from device-tree. > Please let me know your views. Thanks for your comments! The flexspi controller in Layerscape support 8bit DTR, but for flexspi, if support 8bit DTR, need to use mode3, which means we must connect the DQS pad on board. Seems LX216x board do not connect DQS line. We should take this into consideration, this is board limitation, better to involve a property in device-tree. I will send a V2 patch soon. Best Regards Haibo Chen > > Regards > Kuldeep
> -----Original Message----- > From: Bough Chen <haibo.chen@nxp.com> > Sent: Wednesday, September 1, 2021 1:35 PM > To: Kuldeep Singh <kuldeep.singh@nxp.com> > Cc: linux-spi@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>; Rajesh > Bhagat <rajesh.bhagat@nxp.com>; broonie@kernel.org > Subject: RE: [EXT] [PATCH 3/4] spi: spi-nxp-fspi: add DDR mode support > > > -----Original Message----- > > From: Kuldeep Singh > > Sent: 2021年8月31日 18:42 > > To: Bough Chen <haibo.chen@nxp.com> > > Cc: linux-spi@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>; Bough > Chen > > <haibo.chen@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>; > > broonie@kernel.org > > Subject: RE: [EXT] [PATCH 3/4] spi: spi-nxp-fspi: add DDR mode support > > > > Hi Haibo, > > > > > -----Original Message----- > > > From: haibo.chen@nxp.com <haibo.chen@nxp.com> > > > Sent: Friday, August 20, 2021 1:14 PM > > > To: Ashish Kumar <ashish.kumar@nxp.com>; yogeshgaur.83@gmail.com; > > > broonie@kernel.org > > > Cc: linux-spi@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>; Bough > > > Chen <haibo.chen@nxp.com> > > > Subject: [EXT] [PATCH 3/4] spi: spi-nxp-fspi: add DDR mode support > > > > > > Caution: EXT Email > > > > > > From: Haibo Chen <haibo.chen@nxp.com> > > > > > > For LUT, add DDR command support. > > > Also use new API spi_mem_dtr_supports_op() to check the DTR mode. > > > > > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> > > > > Thanks for submitting patch to support octal DTR. > > > > > --- > > > drivers/spi/spi-nxp-fspi.c | 25 ++++++++++++++++++++----- > > > 1 file changed, 20 insertions(+), 5 deletions(-) > > > > > > diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c > > > index > > > a764eb475aed..f7acad2cbe64 100644 > > > --- a/drivers/spi/spi-nxp-fspi.c > > > +++ b/drivers/spi/spi-nxp-fspi.c > > > @@ -486,6 +486,9 @@ static bool nxp_fspi_supports_op(struct spi_mem > > > *mem, > > > op->data.nbytes > f->devtype_data->txfifo) > > > return false; > > > > > > + if (op->cmd.dtr && op->addr.dtr && op->dummy.dtr && > > op->data.dtr) > > > + return spi_mem_dtr_supports_op(mem, op); > > > + > > [snip] > > > > Now that spi-nor framework and flexspi driver supports octal DTR, if > > device-tree specifies RX and TX bus-width as <8,8> , then above change > will > > always make sure to select DTR mode and SDR will never get selected. > > Please note, Layerscape LX2160A and LX2162A are two platforms which have > > micron mt35xu512aba (support octal dtr) and are causing probe failure with > > these patches as required dependencies for enabling DTR are not met. > > > > Since framework selects maximum supported capability, I think there should > be > > a mechanism to choose SDR or DTR mode in driver itself. > > This will also help for a platform to fallback from DTR to SDR in case DTR > > doesn't work. > > We can enable this feature as a quirk or by reading a property from > device-tree. > > Please let me know your views. > > Thanks for your comments! > The flexspi controller in Layerscape support 8bit DTR, but for flexspi, if > support 8bit DTR, need to use mode3, which means we must connect the DQS > pad > on board. > Seems LX216x board do not connect DQS line. > We should take this into consideration, this is board limitation, better to > involve a property in device-tree. > I will send a V2 patch soon. Thanks for your understanding. I will make sure to confirm NXP layerscape devices for next version of series. Regards Kuldeep
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index a764eb475aed..f7acad2cbe64 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -486,6 +486,9 @@ static bool nxp_fspi_supports_op(struct spi_mem *mem, op->data.nbytes > f->devtype_data->txfifo) return false; + if (op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr) + return spi_mem_dtr_supports_op(mem, op); + return spi_mem_default_supports_op(mem, op); } @@ -534,12 +537,22 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f, int lutidx = 1, i; /* cmd */ - lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), - op->cmd.opcode); + if (op->cmd.dtr) { + lutval[0] |= LUT_DEF(0, LUT_CMD_DDR, LUT_PAD(op->cmd.buswidth), + op->cmd.opcode >> 8); + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_CMD_DDR, + LUT_PAD(op->cmd.buswidth), + op->cmd.opcode & 0x00ff); + lutidx++; + } else { + lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), + op->cmd.opcode); + } /* addr bytes */ if (op->addr.nbytes) { - lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, + lutval[lutidx / 2] |= LUT_DEF(lutidx, op->addr.dtr ? + LUT_ADDR_DDR : LUT_ADDR, LUT_PAD(op->addr.buswidth), op->addr.nbytes * 8); lutidx++; @@ -547,7 +560,8 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f, /* dummy bytes, if needed */ if (op->dummy.nbytes) { - lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, + lutval[lutidx / 2] |= LUT_DEF(lutidx, op->dummy.dtr ? + LUT_DUMMY_DDR : LUT_DUMMY, /* * Due to FlexSPI controller limitation number of PAD for dummy * buswidth needs to be programmed as equal to data buswidth. @@ -562,7 +576,8 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f, if (op->data.nbytes) { lutval[lutidx / 2] |= LUT_DEF(lutidx, op->data.dir == SPI_MEM_DATA_IN ? - LUT_NXP_READ : LUT_NXP_WRITE, + (op->data.dtr ? LUT_READ_DDR : LUT_NXP_READ) : + (op->data.dtr ? LUT_WRITE_DDR : LUT_NXP_WRITE), LUT_PAD(op->data.buswidth), 0); lutidx++;