| Message ID | 20210824104041.708945-3-tanureal@opensource.cirrus.com |
|---|---|
| State | New |
| Headers | show |
| Series | Improve support for AMD SPI controllers | expand |
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 8371bca13729..f5b55c237634 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -514,6 +514,7 @@ struct spi_controller { #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */ #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ +#define SPI_CONTROLLER_CS_PER_TRANSFER BIT(6) /* SPI controller can not hold CS between transfers */ /* flag indicating if the allocation of this struct is devres-managed */ bool devm_allocated;
Create a flag for a controller that has an automatic cs selection and can't hold cs activated between transfers Some messages send address and data split between two transfers, see regmap-spi, and without the cs held the data loses it`s meaning Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> --- include/linux/spi/spi.h | 1 + 1 file changed, 1 insertion(+)