From patchwork Tue Jun 23 10:09:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 50211 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f199.google.com (mail-lb0-f199.google.com [209.85.217.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id C39E8216E1 for ; Tue, 23 Jun 2015 10:10:32 +0000 (UTC) Received: by lbcui10 with SMTP id ui10sf1610836lbc.0 for ; Tue, 23 Jun 2015 03:10:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=ITkmBKprXUha8oFq6ZpVRzwNDp3CWsW2EqWSb2UR1Wg=; b=fSBu//AdaVMeVmdbv1fB0Wk4EmjU6PO8zWwoRd3kHZuFE6MWRsMLB3qQaojWFoqT9I PZFhu1CB1WuTRMMs4wezYG73cix936PwbqVVXvnA6r8yM/J7mKYxemMmSf+Kh016FnVi xhNsLHvpCfvyLjaU3B2F8XKaXXfONa1cUwxFhh8jxsCXqtYH0UU5osfuFzoUTRfW6izS NgSawBe3ARSaaHjNCZBWy+TltWRJKWGzpvliXaL2ZEUIe8G7o0pbyYuw09PxnaSdGv7t VKuNGVBPqw3jE5LZRU0xQR7/troCcAo26NAyhGqTLkGJEx+NkkViO+AwimCLlo5NvWGK jdCQ== X-Gm-Message-State: ALoCoQknIXfVtfIHJXS7AkP7u8ufpl2VGaU/BEP6yMD7cR6F96VJgKeE+S0QzFci42P3/SclBCTG X-Received: by 10.112.26.5 with SMTP id h5mr31698791lbg.4.1435054231721; Tue, 23 Jun 2015 03:10:31 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.6.130 with SMTP id b2ls28096laa.4.gmail; Tue, 23 Jun 2015 03:10:31 -0700 (PDT) X-Received: by 10.152.10.104 with SMTP id h8mr3805425lab.23.1435054231572; Tue, 23 Jun 2015 03:10:31 -0700 (PDT) Received: from mail-lb0-f170.google.com (mail-lb0-f170.google.com. [209.85.217.170]) by mx.google.com with ESMTPS id pl9si18903160lbb.111.2015.06.23.03.10.31 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Jun 2015 03:10:31 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.170 as permitted sender) client-ip=209.85.217.170; Received: by lbbpo10 with SMTP id po10so3414598lbb.3 for ; Tue, 23 Jun 2015 03:10:31 -0700 (PDT) X-Received: by 10.152.42.177 with SMTP id p17mr12823344lal.29.1435054231322; Tue, 23 Jun 2015 03:10:31 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp2963363lbb; Tue, 23 Jun 2015 03:10:30 -0700 (PDT) X-Received: by 10.70.90.133 with SMTP id bw5mr68016609pdb.85.1435054227925; Tue, 23 Jun 2015 03:10:27 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h8si33982278pdn.89.2015.06.23.03.10.27 for ; Tue, 23 Jun 2015 03:10:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932666AbbFWKKZ (ORCPT ); Tue, 23 Jun 2015 06:10:25 -0400 Received: from mail-pd0-f169.google.com ([209.85.192.169]:36741 "EHLO mail-pd0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753865AbbFWKKU (ORCPT ); Tue, 23 Jun 2015 06:10:20 -0400 Received: by pdcu2 with SMTP id u2so4229433pdc.3 for ; Tue, 23 Jun 2015 03:10:19 -0700 (PDT) X-Received: by 10.66.145.33 with SMTP id sr1mr66596420pab.41.1435054219744; Tue, 23 Jun 2015 03:10:19 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.178]) by mx.google.com with ESMTPSA id cq5sm4063415pad.11.2015.06.23.03.10.12 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Jun 2015 03:10:18 -0700 (PDT) From: Jun Nie To: peter@hurleysoftware.com, linux@arm.linux.org.uk, Andrew.Jackson@arm.com, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, shawn.guo@linaro.org Cc: jason.liu@linaro.org, wan.zhijun@zte.com.cn, Jun Nie Subject: [PATCH v12 3/5] uart: pl011: Introduce register look up table Date: Tue, 23 Jun 2015 18:09:33 +0800 Message-Id: <1435054175-7473-4-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1435054175-7473-1-git-send-email-jun.nie@linaro.org> References: <1435054175-7473-1-git-send-email-jun.nie@linaro.org> Sender: linux-serial-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-serial@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jun.nie@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Introduce register look up table as different SOC venders may have different register offset for the some register. Signed-off-by: Jun Nie Reviewed-by: Peter Hurley --- drivers/tty/serial/amba-pl011.c | 53 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 305c04b..6a16006 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -76,6 +76,7 @@ struct vendor_data { unsigned int ifls; unsigned int lcrh_tx; unsigned int lcrh_rx; + u16 *reg_lut; bool oversampling; bool dma_threshold; bool cts_event_workaround; @@ -105,6 +106,25 @@ enum reg_idx { REG_DMACR = IDX(UART011_DMACR), }; +static u16 arm_reg[] = { + [REG_DR] = UART01x_DR, + [REG_RSR] = UART01x_RSR, + [REG_ST_DMAWM] = ~0, + [REG_FR] = UART01x_FR, + [REG_ST_LCRH_RX] = ~0, + [REG_ILPR] = UART01x_ILPR, + [REG_IBRD] = UART011_IBRD, + [REG_FBRD] = UART011_FBRD, + [REG_LCRH] = UART011_LCRH, + [REG_CR] = UART011_CR, + [REG_IFLS] = UART011_IFLS, + [REG_IMSC] = UART011_IMSC, + [REG_RIS] = UART011_RIS, + [REG_MIS] = UART011_MIS, + [REG_ICR] = UART011_ICR, + [REG_DMACR] = UART011_DMACR, +}; + static unsigned int get_fifosize_arm(struct amba_device *dev) { return amba_rev(dev) < 3 ? 16 : 32; @@ -114,12 +134,32 @@ static struct vendor_data vendor_arm = { .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, .lcrh_tx = REG_LCRH, .lcrh_rx = REG_LCRH, + .reg_lut = arm_reg, .oversampling = false, .dma_threshold = false, .cts_event_workaround = false, .get_fifosize = get_fifosize_arm, }; +static u16 st_reg[] = { + [REG_DR] = UART01x_DR, + [REG_RSR] = UART01x_RSR, + [REG_ST_DMAWM] = ST_UART011_DMAWM, + [REG_FR] = UART01x_FR, + [REG_ST_LCRH_RX] = ST_UART011_LCRH_RX, + [REG_ILPR] = UART01x_ILPR, + [REG_IBRD] = UART011_IBRD, + [REG_FBRD] = UART011_FBRD, + [REG_LCRH] = UART011_LCRH, + [REG_CR] = UART011_CR, + [REG_IFLS] = UART011_IFLS, + [REG_IMSC] = UART011_IMSC, + [REG_RIS] = UART011_RIS, + [REG_MIS] = UART011_MIS, + [REG_ICR] = UART011_ICR, + [REG_DMACR] = UART011_DMACR, +}; + static unsigned int get_fifosize_st(struct amba_device *dev) { return 64; @@ -129,6 +169,7 @@ static struct vendor_data vendor_st = { .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, .lcrh_tx = REG_LCRH, .lcrh_rx = REG_ST_LCRH_RX, + .reg_lut = st_reg, .oversampling = true, .dma_threshold = true, .cts_event_workaround = true, @@ -172,6 +213,7 @@ struct uart_amba_port { struct uart_port port; struct clk *clk; const struct vendor_data *vendor; + u16 *reg_lut; unsigned int dmacr; /* dma control reg */ unsigned int im; /* interrupt mask */ unsigned int old_status; @@ -196,19 +238,19 @@ struct uart_amba_port { static unsigned int pl011_readw(struct uart_amba_port *uap, int index) { WARN_ON(index > REG_NR); - return readw_relaxed(uap->port.membase + (index << 2)); + return readw_relaxed(uap->port.membase + uap->reg_lut[index]); } static void pl011_writew(struct uart_amba_port *uap, int val, int index) { WARN_ON(index > REG_NR); - writew_relaxed(val, uap->port.membase + (index << 2)); + writew_relaxed(val, uap->port.membase + uap->reg_lut[index]); } static void pl011_writeb(struct uart_amba_port *uap, u8 val, int index) { WARN_ON(index > REG_NR); - writeb_relaxed(val, uap->port.membase + (index << 2)); + writeb_relaxed(val, uap->port.membase + uap->reg_lut[index]); } /* @@ -311,7 +353,7 @@ static void pl011_dma_probe(struct uart_amba_port *uap) struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); struct device *dev = uap->port.dev; struct dma_slave_config tx_conf = { - .dst_addr = uap->port.mapbase + REG_DR, + .dst_addr = uap->port.mapbase + uap->reg_lut[REG_DR], .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, .direction = DMA_MEM_TO_DEV, .dst_maxburst = uap->fifosize >> 1, @@ -366,7 +408,7 @@ static void pl011_dma_probe(struct uart_amba_port *uap) if (chan) { struct dma_slave_config rx_conf = { - .src_addr = uap->port.mapbase + REG_DR, + .src_addr = uap->port.mapbase + uap->reg_lut[REG_DR], .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, .direction = DMA_DEV_TO_MEM, .src_maxburst = uap->fifosize >> 2, @@ -2271,6 +2313,7 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) return PTR_ERR(uap->clk); uap->vendor = vendor; + uap->reg_lut = vendor->reg_lut; uap->lcrh_rx = vendor->lcrh_rx; uap->lcrh_tx = vendor->lcrh_tx; uap->old_cr = 0;