diff mbox series

[bpf-next,03/13] bpf/tests: Add exhaustive tests of ALU shift values

Message ID 20210902185229.1840281-4-johan.almbladh@anyfinetworks.com
State Superseded
Headers show
Series bpf/tests: Extend JIT test suite coverage | expand

Commit Message

Johan Almbladh Sept. 2, 2021, 6:52 p.m. UTC 
This patch adds a set of tests for ALU64 and ALU32 shift operations to
verify correctness for all possible values of the shift value. Mainly
intended for JIT testing.

Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
---
 lib/test_bpf.c | 257 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 257 insertions(+)

Comments

kernel test robot Sept. 3, 2021, 6:39 a.m. UTC | #1 
Hi Johan,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on bpf-next/master]

url:    https://github.com/0day-ci/linux/commits/Johan-Almbladh/bpf-tests-Extend-JIT-test-suite-coverage/20210903-025430
base:   https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git master
config: riscv-randconfig-r001-20210903 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project c9948e9254fbb6ea00f66c7b4542311d21e060be)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install riscv cross compiling tool for clang build
        # apt-get install binutils-riscv64-linux-gnu
        # https://github.com/0day-ci/linux/commit/ceabc579a2dfd55d025c0e65dcdb4f8fd313990c
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Johan-Almbladh/bpf-tests-Extend-JIT-test-suite-coverage/20210903-025430
        git checkout ceabc579a2dfd55d025c0e65dcdb4f8fd313990c
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=riscv 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> lib/test_bpf.c:581:10: warning: unsequenced modification and access to 'i' [-Wunsequenced]
                           insn[i++] = BPF_ALU64_IMM(BPF_MOV, R0, i);
                                 ^                                ~
   1 warning generated.


vim +/i +581 lib/test_bpf.c

   507	
   508	/* Test an ALU shift operation for all valid shift values */
   509	static int __bpf_fill_alu_shift(struct bpf_test *self, u8 op,
   510					u8 mode, bool alu32)
   511	{
   512		static const s64 regs[] = {
   513			0x0123456789abcdefLL, /* dword > 0, word < 0 */
   514			0xfedcba9876543210LL, /* dowrd < 0, word > 0 */
   515			0xfedcba0198765432LL, /* dowrd < 0, word < 0 */
   516			0x0123458967abcdefLL, /* dword > 0, word > 0 */
   517		};
   518		int bits = alu32 ? 32 : 64;
   519		int len = (2 + 8 * bits) * ARRAY_SIZE(regs) + 2;
   520		struct bpf_insn *insn;
   521		int imm, k;
   522		int i = 0;
   523	
   524		insn = kmalloc_array(len, sizeof(*insn), GFP_KERNEL);
   525		if (!insn)
   526			return -ENOMEM;
   527	
   528		for (k = 0; k < ARRAY_SIZE(regs); k++) {
   529			s64 reg = regs[k];
   530	
   531			i += __bpf_ld_imm64(&insn[i], R3, reg);
   532	
   533			for (imm = 0; imm < bits; imm++) {
   534				u64 val;
   535	
   536				/* Perform operation */
   537				insn[i++] = BPF_ALU64_REG(BPF_MOV, R1, R3);
   538				insn[i++] = BPF_ALU64_IMM(BPF_MOV, R2, imm);
   539				if (alu32) {
   540					if (mode == BPF_K)
   541						insn[i++] = BPF_ALU32_IMM(op, R1, imm);
   542					else
   543						insn[i++] = BPF_ALU32_REG(op, R1, R2);
   544					switch (op) {
   545					case BPF_LSH:
   546						val = (u32)reg << imm;
   547						break;
   548					case BPF_RSH:
   549						val = (u32)reg >> imm;
   550						break;
   551					case BPF_ARSH:
   552						val = (u32)reg >> imm;
   553						if (imm > 0 && (reg & 0x80000000))
   554							val |= ~(u32)0 << (32 - imm);
   555						break;
   556					}
   557				} else {
   558					if (mode == BPF_K)
   559						insn[i++] = BPF_ALU64_IMM(op, R1, imm);
   560					else
   561						insn[i++] = BPF_ALU64_REG(op, R1, R2);
   562					switch (op) {
   563					case BPF_LSH:
   564						val = (u64)reg << imm;
   565						break;
   566					case BPF_RSH:
   567						val = (u64)reg >> imm;
   568						break;
   569					case BPF_ARSH:
   570						val = (u64)reg >> imm;
   571						if (imm > 0 && reg < 0)
   572							val |= ~(u64)0 << (64 - imm);
   573						break;
   574					}
   575				}
   576	
   577				/* Load reference */
   578				i += __bpf_ld_imm64(&insn[i], R4, val);
   579	
   580				/* For diagnostic purposes */
 > 581				insn[i++] = BPF_ALU64_IMM(BPF_MOV, R0, i);
   582	
   583				/* Check result */
   584				insn[i++] = BPF_JMP_REG(BPF_JEQ, R1, R4, 1);
   585				insn[i++] = BPF_EXIT_INSN();
   586			}
   587		}
   588	
   589		insn[i++] = BPF_ALU64_IMM(BPF_MOV, R0, 1);
   590		insn[i++] = BPF_EXIT_INSN();
   591	
   592		self->u.ptr.insns = insn;
   593		self->u.ptr.len = len;
   594		BUG_ON(i > len);
   595	
   596		return 0;
   597	}
   598	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff mbox series

Patch

diff --git a/lib/test_bpf.c b/lib/test_bpf.c
index f0651dc6450b..69f8d4c1df33 100644
--- a/lib/test_bpf.c
+++ b/lib/test_bpf.c
@@ -497,6 +497,165 @@  static int bpf_fill_long_jmp(struct bpf_test *self)
 	return 0;
 }
 
+static int __bpf_ld_imm64(struct bpf_insn insns[2], u8 reg, s64 imm64)
+{
+	struct bpf_insn tmp[] = {BPF_LD_IMM64(reg, imm64)};
+
+	memcpy(insns, tmp, sizeof(tmp));
+	return 2;
+}
+
+/* Test an ALU shift operation for all valid shift values */
+static int __bpf_fill_alu_shift(struct bpf_test *self, u8 op,
+				u8 mode, bool alu32)
+{
+	static const s64 regs[] = {
+		0x0123456789abcdefLL, /* dword > 0, word < 0 */
+		0xfedcba9876543210LL, /* dowrd < 0, word > 0 */
+		0xfedcba0198765432LL, /* dowrd < 0, word < 0 */
+		0x0123458967abcdefLL, /* dword > 0, word > 0 */
+	};
+	int bits = alu32 ? 32 : 64;
+	int len = (2 + 8 * bits) * ARRAY_SIZE(regs) + 2;
+	struct bpf_insn *insn;
+	int imm, k;
+	int i = 0;
+
+	insn = kmalloc_array(len, sizeof(*insn), GFP_KERNEL);
+	if (!insn)
+		return -ENOMEM;
+
+	for (k = 0; k < ARRAY_SIZE(regs); k++) {
+		s64 reg = regs[k];
+
+		i += __bpf_ld_imm64(&insn[i], R3, reg);
+
+		for (imm = 0; imm < bits; imm++) {
+			u64 val;
+
+			/* Perform operation */
+			insn[i++] = BPF_ALU64_REG(BPF_MOV, R1, R3);
+			insn[i++] = BPF_ALU64_IMM(BPF_MOV, R2, imm);
+			if (alu32) {
+				if (mode == BPF_K)
+					insn[i++] = BPF_ALU32_IMM(op, R1, imm);
+				else
+					insn[i++] = BPF_ALU32_REG(op, R1, R2);
+				switch (op) {
+				case BPF_LSH:
+					val = (u32)reg << imm;
+					break;
+				case BPF_RSH:
+					val = (u32)reg >> imm;
+					break;
+				case BPF_ARSH:
+					val = (u32)reg >> imm;
+					if (imm > 0 && (reg & 0x80000000))
+						val |= ~(u32)0 << (32 - imm);
+					break;
+				}
+			} else {
+				if (mode == BPF_K)
+					insn[i++] = BPF_ALU64_IMM(op, R1, imm);
+				else
+					insn[i++] = BPF_ALU64_REG(op, R1, R2);
+				switch (op) {
+				case BPF_LSH:
+					val = (u64)reg << imm;
+					break;
+				case BPF_RSH:
+					val = (u64)reg >> imm;
+					break;
+				case BPF_ARSH:
+					val = (u64)reg >> imm;
+					if (imm > 0 && reg < 0)
+						val |= ~(u64)0 << (64 - imm);
+					break;
+				}
+			}
+
+			/* Load reference */
+			i += __bpf_ld_imm64(&insn[i], R4, val);
+
+			/* For diagnostic purposes */
+			insn[i++] = BPF_ALU64_IMM(BPF_MOV, R0, i);
+
+			/* Check result */
+			insn[i++] = BPF_JMP_REG(BPF_JEQ, R1, R4, 1);
+			insn[i++] = BPF_EXIT_INSN();
+		}
+	}
+
+	insn[i++] = BPF_ALU64_IMM(BPF_MOV, R0, 1);
+	insn[i++] = BPF_EXIT_INSN();
+
+	self->u.ptr.insns = insn;
+	self->u.ptr.len = len;
+	BUG_ON(i > len);
+
+	return 0;
+}
+
+static int bpf_fill_alu_lsh_imm(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_LSH, BPF_K, false);
+}
+
+static int bpf_fill_alu_rsh_imm(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_RSH, BPF_K, false);
+}
+
+static int bpf_fill_alu_arsh_imm(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_ARSH, BPF_K, false);
+}
+
+static int bpf_fill_alu_lsh_reg(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_LSH, BPF_X, false);
+}
+
+static int bpf_fill_alu_rsh_reg(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_RSH, BPF_X, false);
+}
+
+static int bpf_fill_alu_arsh_reg(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_ARSH, BPF_X, false);
+}
+
+static int bpf_fill_alu32_lsh_imm(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_LSH, BPF_K, true);
+}
+
+static int bpf_fill_alu32_rsh_imm(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_RSH, BPF_K, true);
+}
+
+static int bpf_fill_alu32_arsh_imm(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_ARSH, BPF_K, true);
+}
+
+static int bpf_fill_alu32_lsh_reg(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_LSH, BPF_X, true);
+}
+
+static int bpf_fill_alu32_rsh_reg(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_RSH, BPF_X, true);
+}
+
+static int bpf_fill_alu32_arsh_reg(struct bpf_test *self)
+{
+	return __bpf_fill_alu_shift(self, BPF_ARSH, BPF_X, true);
+}
+
 static struct bpf_test tests[] = {
 	{
 		"TAX",
@@ -8414,6 +8573,104 @@  static struct bpf_test tests[] = {
 		{},
 		{ { 0, 2 } },
 	},
+	/* Exhaustive test of ALU64 shift operations */
+	{
+		"ALU64_LSH_K: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu_lsh_imm,
+	},
+	{
+		"ALU64_RSH_K: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu_rsh_imm,
+	},
+	{
+		"ALU64_ARSH_K: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu_arsh_imm,
+	},
+	{
+		"ALU64_LSH_X: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu_lsh_reg,
+	},
+	{
+		"ALU64_RSH_X: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu_rsh_reg,
+	},
+	{
+		"ALU64_ARSH_X: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu_arsh_reg,
+	},
+	/* Exhaustive test of ALU32 shift operations */
+	{
+		"ALU32_LSH_K: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu32_lsh_imm,
+	},
+	{
+		"ALU32_RSH_K: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu32_rsh_imm,
+	},
+	{
+		"ALU32_ARSH_K: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu32_arsh_imm,
+	},
+	{
+		"ALU32_LSH_X: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu32_lsh_reg,
+	},
+	{
+		"ALU32_RSH_X: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu32_rsh_reg,
+	},
+	{
+		"ALU32_ARSH_X: all shift values",
+		{ },
+		INTERNAL | FLAG_NO_DATA,
+		{ },
+		{ { 0, 1 } },
+		.fill_helper = bpf_fill_alu32_arsh_reg,
+	},
 };
 
 static struct net_device dev;