| Message ID | 20210908150001.3702552-2-ray.huang@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | [01/19] x86/cpufreatures: add AMD CPPC extension feature flag | expand |
On 9/8/21 8:59 AM, Huang Rui wrote: > Add Collaborative Processor Performance Control Extension feature flag > for AMD processors. > Please add a couple of sentences about the feature and what it does. > Signed-off-by: Huang Rui <ray.huang@amd.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index d0ce5cfd3ac1..f7aea50e3371 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -313,6 +313,7 @@ > #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ > #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ > #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ > +#define X86_FEATURE_AMD_CPPC_EXT (13*32+27) /* Collaborative Processor Performance Control Extension */ > > /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ > #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ > thanks, -- Shuah
On Thu, Sep 09, 2021 at 04:00:04AM +0800, Shuah Khan wrote: > On 9/8/21 8:59 AM, Huang Rui wrote: > > Add Collaborative Processor Performance Control Extension feature flag > > for AMD processors. > > > > Please add a couple of sentences about the feature and what it does. OK, will describe details at V2. Thanks, Ray
On Wed, Sep 08, 2021 at 10:59:43PM +0800, Huang Rui wrote: > Add Collaborative Processor Performance Control Extension feature flag > for AMD processors. > > Signed-off-by: Huang Rui <ray.huang@amd.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index d0ce5cfd3ac1..f7aea50e3371 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -313,6 +313,7 @@ > #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ > #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ > #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ > +#define X86_FEATURE_AMD_CPPC_EXT (13*32+27) /* Collaborative Processor Performance Control Extension */ Why not simply X86_FEATURE_AMD_CPPC ? -- Regards/Gruss, Boris. SUSE Software Solutions Germany GmbH, GF: Felix Imendörffer, HRB 36809, AG Nürnberg
Hi Boris, On Fri, Sep 10, 2021 at 01:58:19AM +0800, Borislav Petkov wrote: > On Wed, Sep 08, 2021 at 10:59:43PM +0800, Huang Rui wrote: > > Add Collaborative Processor Performance Control Extension feature flag > > for AMD processors. > > > > Signed-off-by: Huang Rui <ray.huang@amd.com> > > --- > > arch/x86/include/asm/cpufeatures.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > > index d0ce5cfd3ac1..f7aea50e3371 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -313,6 +313,7 @@ > > #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ > > #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ > > #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ > > +#define X86_FEATURE_AMD_CPPC_EXT (13*32+27) /* Collaborative Processor Performance Control Extension */ > > Why not simply X86_FEATURE_AMD_CPPC ? This feature flag indicates the full MSR hardware solution of AMD P-States, if it is not set, that means we will go with in shared memory hardware solution. So we name this as extension. I will explain the details in the commit log at V2. ;-) Thanks, Ray
On Mon, Sep 13, 2021 at 05:48:51PM +0800, Huang Rui wrote: > This feature flag indicates the full MSR hardware solution of AMD > P-States, if it is not set, that means we will go with in shared > memory hardware solution. So we name this as extension. Nobody cares whether it is an extension except you guys. Also, having AMD_CPPC_EXT suggests there already is AMD_CPPC. But there isn't. So call it X86_FEATURE_AMD_CPPC, please, for simplicity's sake. Thx. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette
On Mon, Sep 13, 2021 at 09:04:42PM +0800, Borislav Petkov wrote: > On Mon, Sep 13, 2021 at 05:48:51PM +0800, Huang Rui wrote: > > This feature flag indicates the full MSR hardware solution of AMD > > P-States, if it is not set, that means we will go with in shared > > memory hardware solution. So we name this as extension. > > Nobody cares whether it is an extension except you guys. Also, having > AMD_CPPC_EXT suggests there already is AMD_CPPC. But there isn't. > > So call it X86_FEATURE_AMD_CPPC, please, for simplicity's sake. > OK, no problem. I will update this in V2. Thanks, Ray
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index d0ce5cfd3ac1..f7aea50e3371 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -313,6 +313,7 @@ #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ +#define X86_FEATURE_AMD_CPPC_EXT (13*32+27) /* Collaborative Processor Performance Control Extension */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
Add Collaborative Processor Performance Control Extension feature flag for AMD processors. Signed-off-by: Huang Rui <ray.huang@amd.com> --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+)