| Message ID | 20211206095921.33302-3-miquel.raynal@bootlin.com |
|---|---|
| State | New |
| Headers | show |
| Series | Stacked/parallel memories bindings | expand |
On Mon, Dec 06, 2021 at 10:59:20AM +0100, Miquel Raynal wrote: > Describe two new memories modes: > - A stacked mode when the bus is common but the address space extended > with an additinals wires. > - A parallel mode with parallel busses accessing parallel flashes where > the data is spread. > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > --- > .../bindings/spi/spi-peripheral-props.yaml | 21 +++++++++++++++++++ > 1 file changed, 21 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org>
Hi Rob, robh@kernel.org wrote on Mon, 6 Dec 2021 15:22:02 -0600: > On Mon, Dec 06, 2021 at 10:59:20AM +0100, Miquel Raynal wrote: > > Describe two new memories modes: > > - A stacked mode when the bus is common but the address space extended > > with an additinals wires. > > - A parallel mode with parallel busses accessing parallel flashes where > > the data is spread. > > > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > > --- > > .../bindings/spi/spi-peripheral-props.yaml | 21 +++++++++++++++++++ > > 1 file changed, 21 insertions(+) > > Reviewed-by: Rob Herring <robh@kernel.org> I am sending a new version of this series so that I can get feedback on other way of describing the flashes, so I'll drop your tag because I'll need you to re-check that I'm not doing anything silly (it took me a while to understand the array vs. matrix logic). Thanks, Miquèl
diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 5dd209206e88..13aa6a2374c9 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -82,6 +82,27 @@ properties: description: Delay, in microseconds, after a write transfer. + stacked-memories: + type: boolean + description: Several SPI memories can be wired in stacked mode. + This basically means that either a device features several chip + selects, or that different devices must be seen as a single + bigger chip. This basically doubles (or more) the total address + space with only a single additional wire, while still needing + to repeat the commands when crossing a chip boundary. XIP is + usually not supported in this mode. + + parallel-memories: + type: boolean + description: Several SPI memories can be wired in parallel mode. + The devices are physically on a different buses but will always + act synchronously as each data word is spread across the + different memories (eg. even bits are stored in one memory, odd + bits in the other). This basically doubles the address space and + the throughput while greatly complexifying the wiring because as + many busses as devices must be wired. XIP is usually not + supported in this mode. + # The controller specific properties go here. allOf: - $ref: cdns,qspi-nor-peripheral-props.yaml#
Describe two new memories modes: - A stacked mode when the bus is common but the address space extended with an additinals wires. - A parallel mode with parallel busses accessing parallel flashes where the data is spread. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- .../bindings/spi/spi-peripheral-props.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+)