| Message ID | 20211217161654.367782-2-miquel.raynal@bootlin.com |
|---|---|
| State | New |
| Headers | show |
| Series | External ECC engines & Macronix support | expand |
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 37f4443ce9a0..c4da0c9b05e9 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -163,7 +163,7 @@ static bool spi_mem_check_buswidth(struct spi_mem *mem, bool spi_mem_dtr_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - if (op->cmd.nbytes != 2) + if (op->cmd.dtr && op->cmd.nbytes != 2) return false; return spi_mem_check_buswidth(mem, op);
It seems that the number of command bytes must be "2" only when the command itself is sent in DTR mode. The current logic checks if the number of command bytes is "2" when any of the cycles is a DTR cycle. It is likely that so far no device was actually mixing DTR/non-DTR cycles in the same operation, explaining why this was left undetected until now. Fixes: 539cf68cd51b ("spi: spi-mem: add spi_mem_dtr_supports_op()") Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/spi/spi-mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)