[v7,5/8] Watchdog: introduce ARM SBSA watchdog driver

Message ID 1440435683-7343-6-git-send-email-fu.wei@linaro.org
State New
Headers show

Commit Message

Fu Wei Aug. 24, 2015, 5:01 p.m.
From: Fu Wei <fu.wei@linaro.org>

This driver bases on linux kernel watchdog framework, and
use "pretimeout" in the framework. It supports getting timeout and
pretimeout from parameter and FDT at the driver init stage.
In first timeout, the interrupt routine run panic to save
system context.

Signed-off-by: Fu Wei <fu.wei@linaro.org>
---
 drivers/watchdog/Kconfig     |  14 ++
 drivers/watchdog/Makefile    |   1 +
 drivers/watchdog/sbsa_gwdt.c | 459 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 474 insertions(+)

Comments

Jon Masters Sept. 10, 2015, 10:29 p.m. | #1
On 08/24/2015 01:01 PM, fu.wei@linaro.org wrote:

> +	/*
> +	 * Get the frequency of system counter from the cp15 interface of ARM
> +	 * Generic timer. We don't need to check it, because if it returns "0",
> +	 * system would panic in very early stage.
> +	 */
> +	gwdt->clk = arch_timer_get_cntfrq();

Just thinking out loud...

What happens later if we virtualize this device within KVM/QEMU/Xen and
then live migrate to another system in which the frequency changes?

Jon.

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Guenter Roeck Sept. 11, 2015, 2:05 a.m. | #2
On Thu, Sep 10, 2015 at 06:29:53PM -0400, Jon Masters wrote:
> On 08/24/2015 01:01 PM, fu.wei@linaro.org wrote:
> 
> > +	/*
> > +	 * Get the frequency of system counter from the cp15 interface of ARM
> > +	 * Generic timer. We don't need to check it, because if it returns "0",
> > +	 * system would panic in very early stage.
> > +	 */
> > +	gwdt->clk = arch_timer_get_cntfrq();
> 
> Just thinking out loud...
> 
> What happens later if we virtualize this device within KVM/QEMU/Xen and
> then live migrate to another system in which the frequency changes?
> 
I don't know, but I would suspect that we might end up in all kinds of
trouble if clocks can change like that, and not just in this driver.
Many drivers make the assumption that clock rates are not changed
under the hood. If it can happen, shouldn't there be a callback into
the drivers using the affected clock(s) ?

Also, it seems to me that changing a clock like that would be inherently
unsafe. For example, what will happen if the system is stopped and migrated
right after the clock frequency is read, but before the returned value
is used ? Can that happen ? Or does it only happen during suspend/resume
cycles, if it happens ?

Thanks,
Guenter
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Guenter Roeck Sept. 11, 2015, 2:50 a.m. | #3
On 09/10/2015 03:29 PM, Jon Masters wrote:
> On 08/24/2015 01:01 PM, fu.wei@linaro.org wrote:
>
>> +	/*
>> +	 * Get the frequency of system counter from the cp15 interface of ARM
>> +	 * Generic timer. We don't need to check it, because if it returns "0",
>> +	 * system would panic in very early stage.
>> +	 */
>> +	gwdt->clk = arch_timer_get_cntfrq();
>
> Just thinking out loud...
>
> What happens later if we virtualize this device within KVM/QEMU/Xen and
> then live migrate to another system in which the frequency changes?
>

Thinking about it, this scenario would cause severe trouble. I think clocks
(like I would assume pretty much all other hardware parameters / registers)
need to be virtualized and must not change.

Example: clock is set to 100 kHz on original system, and 400 kHz on new
system. Timeout is set to 30s, and registers are programmed accordingly.
User space sends heartbeats every 15 seconds.

In this scenario, the watchdog would time out after 30/4 = 7.5 seconds
on the new system, or in other words almost immediately.

This would be even worse if the original system had a clock of, say,
10 kHz and the new system would use 400 kHz. This just doesn't work.

Guenter

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Fu Wei Sept. 14, 2015, 5:11 p.m. | #4
Hi Guenter, Jon,

On 11 September 2015 at 10:50, Guenter Roeck <linux@roeck-us.net> wrote:
> On 09/10/2015 03:29 PM, Jon Masters wrote:
>>
>> On 08/24/2015 01:01 PM, fu.wei@linaro.org wrote:
>>
>>> +       /*
>>> +        * Get the frequency of system counter from the cp15 interface of
>>> ARM
>>> +        * Generic timer. We don't need to check it, because if it
>>> returns "0",
>>> +        * system would panic in very early stage.
>>> +        */
>>> +       gwdt->clk = arch_timer_get_cntfrq();
>>
>>
>> Just thinking out loud...
>>
>> What happens later if we virtualize this device within KVM/QEMU/Xen and
>> then live migrate to another system in which the frequency changes?
>>
>
> Thinking about it, this scenario would cause severe trouble. I think clocks
> (like I would assume pretty much all other hardware parameters / registers)
> need to be virtualized and must not change.
>
> Example: clock is set to 100 kHz on original system, and 400 kHz on new
> system. Timeout is set to 30s, and registers are programmed accordingly.
> User space sends heartbeats every 15 seconds.
>
> In this scenario, the watchdog would time out after 30/4 = 7.5 seconds
> on the new system, or in other words almost immediately.
>
> This would be even worse if the original system had a clock of, say,
> 10 kHz and the new system would use 400 kHz. This just doesn't work.

I have rechecked the SBSA spec and "Architecture Reference Manual(ARM)",
I think we don't need to worry about "the frequency changes", let me
explain this, but if I misunderstand something, please correct me!

(1) what is the clock source (or reference) of SBSA watchdog timer?
SBSA spec(2.3) has answered this well at page 23:
---------------------------
The Watchdog uses the Generic Timer system count value as the timebase
against which the decision to trigger an interrupt is made.
---------------------------

(2) Can the frequency of the Generic Timer System counter be changed?
At ARMv8 ARM,  D6.1.1 System counter :
---------------------------
The Generic Timer provides a system counter with the following specification:
Frequency
Increments at *a fixed frequency*, typically in the range 1-50MHz.
Can support one or more alternative operating modes in which it
increments by larger amounts at a lower frequency, typically for
power-saving.

To support lower-power operating modes, the counter can increment by
larger amounts at a lower frequency. For example, a 10MHz system
counter might either increment either:
• By 1 at 10MHz.
• By 500 at 20kHz,
when the system lowers the clock frequency, to reduce power consumption.
In this case, the counter must support transitions between
high-frequency, high-precision operation, and lower-frequency,
lower-precision operation, without any impact on the required accuracy
of the counter.
---------------------------
So even the frequency of the Generic Timer System counter be changed
by some reason(typically for power-saving), this won't affect the
timeout(and pretimeout) of watchdog, the actual time will be always
right.

*we were talking about real hardware above. Now we think about virtualization.*
(3) if the virtual watchdog device in KVM/QEMU/Xen is migrated to
another system in which the frequency changes, will it affect the "dog
feeding procedure"?

I don't think so.
if the frequency changes, the frequency of System counter is changed.
But in ARM system, System counter is a global reference for all clocks
or timers(per-cpu and Memory-mapped).
So if   System counter is getting faster, everything in this  virtual
machine is getting faster, and vice versa.

Now we use the example above
if  clock is set to 100 kHz on original system, and 400 kHz on new system.
Timeout is set to 30s, and registers are programmed accordingly. User
space sends heartbeats every 15 seconds.
In this scenario, On the new system, the watchdog would time out after
30/4 = 7.5 seconds.
* User space sends heartbeats every 15/4 = 3.25 second now , but NOT
15 seconds.*
If everything goes well,  system will keep running.

Hope I understand the question correctly, please  correct me if I miss
something or said anything wrong.

Great thanks for your feedback!

>
> Guenter
>
Dave Young Sept. 15, 2015, 8:38 a.m. | #5
On 08/25/15 at 01:01am, fu.wei@linaro.org wrote:
> From: Fu Wei <fu.wei@linaro.org>
> 
> This driver bases on linux kernel watchdog framework, and
> use "pretimeout" in the framework. It supports getting timeout and
> pretimeout from parameter and FDT at the driver init stage.
> In first timeout, the interrupt routine run panic to save
> system context.
> 
> Signed-off-by: Fu Wei <fu.wei@linaro.org>
> ---
>  drivers/watchdog/Kconfig     |  14 ++
>  drivers/watchdog/Makefile    |   1 +
>  drivers/watchdog/sbsa_gwdt.c | 459 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 474 insertions(+)
> 
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 241fafd..b2734f0 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -173,6 +173,20 @@ config ARM_SP805_WATCHDOG
>  	  ARM Primecell SP805 Watchdog timer. This will reboot your system when
>  	  the timeout is reached.
>  
> +config ARM_SBSA_WATCHDOG
> +	tristate "ARM SBSA Generic Watchdog"
> +	depends on ARM64
> +	depends on ARM_ARCH_TIMER
> +	select WATCHDOG_CORE
> +	help
> +	  ARM SBSA Generic Watchdog. This watchdog has two Watchdog timeouts.
> +	  The first timeout will trigger a panic; the second timeout will
> +	  trigger a system reset.
> +	  More details: ARM DEN0029B - Server Base System Architecture (SBSA)
> +
> +	  To compile this driver as module, choose M here: The module
> +	  will be called sbsa_gwdt.
> +
>  config AT91RM9200_WATCHDOG
>  	tristate "AT91RM9200 watchdog"
>  	depends on SOC_AT91RM9200 && MFD_SYSCON
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index 59ea9a1..be8e7c5 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -30,6 +30,7 @@ obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
>  
>  # ARM Architecture
>  obj-$(CONFIG_ARM_SP805_WATCHDOG) += sp805_wdt.o
> +obj-$(CONFIG_ARM_SBSA_WATCHDOG) += sbsa_gwdt.o
>  obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
>  obj-$(CONFIG_AT91SAM9X_WATCHDOG) += at91sam9_wdt.o
>  obj-$(CONFIG_CADENCE_WATCHDOG) += cadence_wdt.o
> diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
> new file mode 100644
> index 0000000..7ae45cc
> --- /dev/null
> +++ b/drivers/watchdog/sbsa_gwdt.c
> @@ -0,0 +1,459 @@
> +/*
> + * SBSA(Server Base System Architecture) Generic Watchdog driver
> + *
> + * Copyright (c) 2015, Linaro Ltd.
> + * Author: Fu Wei <fu.wei@linaro.org>
> + *         Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License 2 as published
> + * by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * The SBSA Generic watchdog driver is compatible with the pretimeout
> + * concept of Linux kernel.
> + * The timeout and pretimeout are determined by WCV or WOR.
> + * The first watch period is set by writing WCV directly, that can
> + * support more than 10s timeout at the maximum system counter
> + * frequency (400MHz).
> + * When WS0 is triggered, the second watch period (pretimeout) is
> + * determined by one of these registers:
> + * (1)WOR: 32bit register, this gives a maximum watch period of
> + * around 10s at the maximum system counter frequency. It's loaded
> + * automatically by hardware.
> + * (2)WCV: If the pretimeout value is greater then "max_wor_timeout",
> + * it will be loaded in WS0 interrupt routine. If system is in
> + * ws0_mode (reboot by kexec/kdump in panic with watchdog enabled
> + * and WS0 == true), the ping operation will only reload WCV.

Below is the field comment about ws0_mode, it says ws0_mode is only
for rebooting in second stage timeout, but kexec/kdump can reboot in
either first or second stage
 * @ws0_mode:		indicate the system boot in the second stage timeout.


> + * More details about the hardware specification of this device:
> + * ARM DEN0029B - Server Base System Architecture (SBSA)
> + *
> + * Kernel/API:                         P------------------| pretimeout
> + *               |----------------------------------------T timeout
> + * SBSA GWDT:                          P---WOR (or WCV)---WS1 pretimeout
> + *               |-------WCV----------WS0~~~(ws0_mode)~~~~T timeout
> + */
> +
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/uaccess.h>
> +#include <linux/watchdog.h>
> +#include <asm/arch_timer.h>
> +
> +/* SBSA Generic Watchdog register definitions */
> +/* refresh frame */
> +#define SBSA_GWDT_WRR				0x000
> +
> +/* control frame */
> +#define SBSA_GWDT_WCS				0x000
> +#define SBSA_GWDT_WOR				0x008
> +#define SBSA_GWDT_WCV_LO			0x010
> +#define SBSA_GWDT_WCV_HI			0x014
> +
> +/* refresh/control frame */
> +#define SBSA_GWDT_W_IIDR			0xfcc
> +#define SBSA_GWDT_IDR				0xfd0
> +
> +/* Watchdog Control and Status Register */
> +#define SBSA_GWDT_WCS_EN			BIT(0)
> +#define SBSA_GWDT_WCS_WS0			BIT(1)
> +#define SBSA_GWDT_WCS_WS1			BIT(2)
> +
> +/**
> + * struct sbsa_gwdt - Internal representation of the SBSA GWDT
> + * @wdd:		kernel watchdog_device structure
> + * @clk:		store the System Counter clock frequency, in Hz.
> + * @ws0_mode:		indicate the system boot in the second stage timeout.
> + * @max_wor_timeout:	the maximum timeout value for WOR (in seconds).
> + * @refresh_base:	Virtual address of the watchdog refresh frame
> + * @control_base:	Virtual address of the watchdog control frame
> + */
> +struct sbsa_gwdt {
> +	struct watchdog_device	wdd;
> +	u32			clk;
> +	bool			ws0_mode;
> +	int			max_wor_timeout;
> +	void __iomem		*refresh_base;
> +	void __iomem		*control_base;
> +};
> +
> +#define to_sbsa_gwdt(e) container_of(e, struct sbsa_gwdt, wdd)
> +
> +#define DEFAULT_TIMEOUT		30 /* seconds, the 1st + 2nd watch periods*/
> +#define DEFAULT_PRETIMEOUT	10 /* seconds, the 2nd watch period*/
> +
> +static unsigned int timeout;
> +module_param(timeout, uint, 0);
> +MODULE_PARM_DESC(timeout,
> +		 "Watchdog timeout in seconds. (>=0, default="
> +		 __MODULE_STRING(DEFAULT_TIMEOUT) ")");
> +
> +static unsigned int pretimeout;
> +module_param(pretimeout, uint, 0);
> +MODULE_PARM_DESC(pretimeout,
> +		 "Watchdog pretimeout in seconds. (>=0, default="
> +		 __MODULE_STRING(DEFAULT_PRETIMEOUT) ")");
> +
> +static bool nowayout = WATCHDOG_NOWAYOUT;
> +module_param(nowayout, bool, S_IRUGO);
> +MODULE_PARM_DESC(nowayout,
> +		 "Watchdog cannot be stopped once started (default="
> +		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> +
> +/*
> + * help functions for accessing 64bit WCV register
> + */
> +static u64 sbsa_gwdt_get_wcv(struct watchdog_device *wdd)
> +{
> +	u32 wcv_lo, wcv_hi;
> +	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
> +
> +	do {
> +		wcv_hi = readl_relaxed(gwdt->control_base + SBSA_GWDT_WCV_HI);
> +		wcv_lo = readl_relaxed(gwdt->control_base + SBSA_GWDT_WCV_LO);
> +	} while (wcv_hi != readl_relaxed(gwdt->control_base +
> +					 SBSA_GWDT_WCV_HI));
> +
> +	return (((u64)wcv_hi << 32) | wcv_lo);
> +}
> +
> +static void sbsa_gwdt_set_wcv(struct watchdog_device *wdd, unsigned int t)
> +{
> +	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
> +	u64 wcv;
> +
> +	wcv = arch_counter_get_cntvct() + (u64)t * gwdt->clk;
> +
> +	writel_relaxed(upper_32_bits(wcv),
> +		       gwdt->control_base + SBSA_GWDT_WCV_HI);
> +	writel_relaxed(lower_32_bits(wcv),
> +		       gwdt->control_base + SBSA_GWDT_WCV_LO);
> +}
> +
> +/*
> + * inline functions for reloading 64bit WCV register
> + */
> +static inline void reload_pretimeout_to_wcv(struct watchdog_device *wdd)
> +{
> +	sbsa_gwdt_set_wcv(wdd, wdd->pretimeout);
> +}
> +
> +static inline void reload_first_stage_to_wcv(struct watchdog_device *wdd)
> +{
> +	sbsa_gwdt_set_wcv(wdd, wdd->timeout - wdd->pretimeout);
> +}
> +
> +/*
> + * watchdog operation functions
> + */
> +static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
> +				 unsigned int timeout)
> +{
> +	wdd->timeout = timeout;
> +
> +	return 0;
> +}
> +
> +static int sbsa_gwdt_set_pretimeout(struct watchdog_device *wdd,
> +				    unsigned int pretimeout)
> +{
> +	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
> +	u32 wor;
> +
> +	wdd->pretimeout = pretimeout;
> +
> +	/* If ws0_mode == true, we won't touch WOR */
> +	if (!gwdt->ws0_mode) {
> +		if (!pretimeout)
> +			/*
> +			 * If pretimeout is 0, it gives driver a timeslot (1s)
> +			 * to update WCV after an explicit refresh
> +			 * (sbsa_gwdt_start)
> +			 */
> +			wor = gwdt->clk;
> +		else
> +			if (pretimeout > gwdt->max_wor_timeout)
> +				wor = U32_MAX;
> +			else
> +				wor = pretimeout * gwdt->clk;
> +
> +		/* wtite WOR, that will cause an explicit watchdog refresh */
> +		writel_relaxed(wor, gwdt->control_base + SBSA_GWDT_WOR);
> +	}
> +
> +	return 0;
> +}
> +
> +static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
> +{
> +	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
> +	u64 timeleft = sbsa_gwdt_get_wcv(wdd) - arch_counter_get_cntvct();
> +
> +	do_div(timeleft, gwdt->clk);
> +
> +	return timeleft;
> +}
> +
> +static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
> +{
> +	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
> +
> +	if (gwdt->ws0_mode)
> +		reload_pretimeout_to_wcv(wdd);
> +	else
> +		reload_first_stage_to_wcv(wdd);
> +
> +	return 0;
> +}
> +
> +static int sbsa_gwdt_start(struct watchdog_device *wdd)
> +{
> +	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
> +
> +	/* If ws0_mode == true, the watchdog is enabled */
> +	if (!gwdt->ws0_mode)
> +		/* writing WCS will cause an explicit watchdog refresh */
> +		writel_relaxed(SBSA_GWDT_WCS_EN,
> +			       gwdt->control_base + SBSA_GWDT_WCS);
> +
> +	return sbsa_gwdt_keepalive(wdd);
> +}
> +
> +static int sbsa_gwdt_stop(struct watchdog_device *wdd)
> +{
> +	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
> +
> +	writel_relaxed(0, gwdt->control_base + SBSA_GWDT_WCS);
> +	/*
> +	 * Writing WCS has caused an explicit watchdog refresh.
> +	 * Both watchdog signals are deasserted, so clean ws0_mode flag.
> +	 */
> +	gwdt->ws0_mode = false;
> +
> +	return 0;
> +}
> +
> +static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
> +{
> +	struct sbsa_gwdt *gwdt = (struct sbsa_gwdt *)dev_id;
> +	struct watchdog_device *wdd = &gwdt->wdd;
> +
> +	/* We don't use pretimeout, trigger WS1 now */
> +	if (!wdd->pretimeout)
> +		sbsa_gwdt_set_wcv(wdd, 0);
> +
> +	/*
> +	 * The pretimeout is valid, go panic
> +	 * If pretimeout is greater then "max_wor_timeout",
> +	 * reload the right value to WCV, then panic
> +	 */
> +	if (wdd->pretimeout > gwdt->max_wor_timeout)
> +		reload_pretimeout_to_wcv(wdd);
> +	panic("SBSA Watchdog pre-timeout");
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct watchdog_info sbsa_gwdt_info = {
> +	.identity	= "SBSA Generic Watchdog",
> +	.options	= WDIOF_SETTIMEOUT |
> +			  WDIOF_KEEPALIVEPING |
> +			  WDIOF_MAGICCLOSE |
> +			  WDIOF_PRETIMEOUT |
> +			  WDIOF_CARDRESET,
> +};
> +
> +static struct watchdog_ops sbsa_gwdt_ops = {
> +	.owner		= THIS_MODULE,
> +	.start		= sbsa_gwdt_start,
> +	.stop		= sbsa_gwdt_stop,
> +	.ping		= sbsa_gwdt_keepalive,
> +	.set_timeout	= sbsa_gwdt_set_timeout,
> +	.set_pretimeout	= sbsa_gwdt_set_pretimeout,
> +	.get_timeleft	= sbsa_gwdt_get_timeleft,
> +};
> +
> +static int sbsa_gwdt_probe(struct platform_device *pdev)
> +{
> +	void __iomem *rf_base, *cf_base;
> +	struct device *dev = &pdev->dev;
> +	struct watchdog_device *wdd;
> +	struct sbsa_gwdt *gwdt;
> +	struct resource *res;
> +	int ret, irq;
> +	u32 status;
> +
> +	gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
> +	if (!gwdt)
> +		return -ENOMEM;
> +	platform_set_drvdata(pdev, gwdt);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	cf_base = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(cf_base))
> +		return PTR_ERR(cf_base);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +	rf_base = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(rf_base))
> +		return PTR_ERR(rf_base);
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0) {
> +		dev_err(dev, "unable to get ws0 interrupt.\n");
> +		return irq;
> +	}
> +
> +	/*
> +	 * Get the frequency of system counter from the cp15 interface of ARM
> +	 * Generic timer. We don't need to check it, because if it returns "0",
> +	 * system would panic in very early stage.
> +	 */
> +	gwdt->clk = arch_timer_get_cntfrq();
> +	gwdt->refresh_base = rf_base;
> +	gwdt->control_base = cf_base;
> +	gwdt->max_wor_timeout = U32_MAX / gwdt->clk;
> +	gwdt->ws0_mode = false;
> +
> +	wdd = &gwdt->wdd;
> +	wdd->parent = dev;
> +	wdd->info = &sbsa_gwdt_info;
> +	wdd->ops = &sbsa_gwdt_ops;
> +	watchdog_set_drvdata(wdd, gwdt);
> +	watchdog_set_nowayout(wdd, nowayout);
> +
> +	wdd->min_pretimeout = 0;
> +	wdd->min_timeout = 1;
> +
> +	/*
> +	 * Because the maximum of gwdt->clk is 400MHz and the maximum of WCV is
> +	 * U64_MAX, so the result of (U64_MAX / gwdt->clk) is always greater
> +	 * than U32_MAX. And the maximum of "unsigned int" is U32_MAX on ARM64.
> +	 * So we set the maximum value of pretimeout and timeout below.
> +	 */
> +	wdd->max_pretimeout = U32_MAX - 1;
> +	wdd->max_timeout = U32_MAX;
> +
> +	wdd->pretimeout = DEFAULT_PRETIMEOUT;
> +	wdd->timeout = DEFAULT_TIMEOUT;
> +	watchdog_init_timeouts(wdd, pretimeout, timeout, dev);
> +
> +	status = readl_relaxed(gwdt->control_base + SBSA_GWDT_WCS);
> +	if (status & SBSA_GWDT_WCS_WS1) {
> +		dev_warn(dev, "System reset by WDT.\n");
> +		wdd->bootstatus |= WDIOF_CARDRESET;
> +	} else if (status == (SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_EN)) {
> +		gwdt->ws0_mode = true;
> +	}
> +
> +	ret = devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0,
> +			       pdev->name, gwdt);
> +	if (ret) {
> +		dev_err(dev, "unable to request IRQ %d\n", irq);
> +		return ret;
> +	}
> +
> +	ret = watchdog_register_device(wdd);
> +	if (ret)
> +		return ret;
> +
> +	/* If ws0_mode == true, the line won't update WOR */
> +	sbsa_gwdt_set_pretimeout(wdd, wdd->pretimeout);
> +
> +	/*
> +	 * If watchdog is already enabled, do a ping operation
> +	 * to keep system running
> +	 */
> +	if (status & SBSA_GWDT_WCS_EN)
> +		sbsa_gwdt_keepalive(wdd);
> +
> +	dev_info(dev, "Initialized with %ds timeout, %ds pretimeout @ %u Hz%s\n",
> +		 wdd->timeout, wdd->pretimeout, gwdt->clk,
> +		 status & SBSA_GWDT_WCS_EN ?
> +			gwdt->ws0_mode ? " [second stage]" : " [enabled]" :
> +			"");
> +
> +	return 0;
> +}
> +
> +static void sbsa_gwdt_shutdown(struct platform_device *pdev)
> +{
> +	struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev);
> +
> +	sbsa_gwdt_stop(&gwdt->wdd);
> +}
> +
> +static int sbsa_gwdt_remove(struct platform_device *pdev)
> +{
> +	struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev);
> +
> +	watchdog_unregister_device(&gwdt->wdd);
> +
> +	return 0;
> +}
> +
> +/* Disable watchdog if it is active during suspend */
> +static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
> +{
> +	struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
> +
> +	if (watchdog_active(&gwdt->wdd))
> +		sbsa_gwdt_stop(&gwdt->wdd);
> +
> +	return 0;
> +}
> +
> +/* Enable watchdog and configure it if necessary */
> +static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
> +{
> +	struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
> +
> +	if (watchdog_active(&gwdt->wdd))
> +		sbsa_gwdt_start(&gwdt->wdd);
> +
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
> +};
> +
> +static const struct of_device_id sbsa_gwdt_of_match[] = {
> +	{ .compatible = "arm,sbsa-gwdt", },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);
> +
> +static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
> +	{ .name = "sbsa-gwdt", },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);
> +
> +static struct platform_driver sbsa_gwdt_driver = {
> +	.driver = {
> +		.name = "sbsa-gwdt",
> +		.pm = &sbsa_gwdt_pm_ops,
> +		.of_match_table = sbsa_gwdt_of_match,
> +	},
> +	.probe = sbsa_gwdt_probe,
> +	.remove = sbsa_gwdt_remove,
> +	.shutdown = sbsa_gwdt_shutdown,
> +	.id_table = sbsa_gwdt_pdev_match,
> +};
> +
> +module_platform_driver(sbsa_gwdt_driver);
> +
> +MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
> +MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
> +MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
> +MODULE_LICENSE("GPL v2");
> -- 
> 2.4.3
> 
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Fu Wei Sept. 15, 2015, 10:07 a.m. | #6
Hi Dave,

On 15 September 2015 at 16:38, Dave Young <dyoung@redhat.com> wrote:
> On 08/25/15 at 01:01am, fu.wei@linaro.org wrote:
>> From: Fu Wei <fu.wei@linaro.org>
>>
>> This driver bases on linux kernel watchdog framework, and
>> use "pretimeout" in the framework. It supports getting timeout and
>> pretimeout from parameter and FDT at the driver init stage.
>> In first timeout, the interrupt routine run panic to save
>> system context.
>>
>> Signed-off-by: Fu Wei <fu.wei@linaro.org>
>> ---
>>  drivers/watchdog/Kconfig     |  14 ++
>>  drivers/watchdog/Makefile    |   1 +
>>  drivers/watchdog/sbsa_gwdt.c | 459 +++++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 474 insertions(+)
>>
>> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
>> index 241fafd..b2734f0 100644
>> --- a/drivers/watchdog/Kconfig
>> +++ b/drivers/watchdog/Kconfig
>> @@ -173,6 +173,20 @@ config ARM_SP805_WATCHDOG
>>         ARM Primecell SP805 Watchdog timer. This will reboot your system when
>>         the timeout is reached.
>>
>> +config ARM_SBSA_WATCHDOG
>> +     tristate "ARM SBSA Generic Watchdog"
>> +     depends on ARM64
>> +     depends on ARM_ARCH_TIMER
>> +     select WATCHDOG_CORE
>> +     help
>> +       ARM SBSA Generic Watchdog. This watchdog has two Watchdog timeouts.
>> +       The first timeout will trigger a panic; the second timeout will
>> +       trigger a system reset.
>> +       More details: ARM DEN0029B - Server Base System Architecture (SBSA)
>> +
>> +       To compile this driver as module, choose M here: The module
>> +       will be called sbsa_gwdt.
>> +
>>  config AT91RM9200_WATCHDOG
>>       tristate "AT91RM9200 watchdog"
>>       depends on SOC_AT91RM9200 && MFD_SYSCON
>> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
>> index 59ea9a1..be8e7c5 100644
>> --- a/drivers/watchdog/Makefile
>> +++ b/drivers/watchdog/Makefile
>> @@ -30,6 +30,7 @@ obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
>>
>>  # ARM Architecture
>>  obj-$(CONFIG_ARM_SP805_WATCHDOG) += sp805_wdt.o
>> +obj-$(CONFIG_ARM_SBSA_WATCHDOG) += sbsa_gwdt.o
>>  obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
>>  obj-$(CONFIG_AT91SAM9X_WATCHDOG) += at91sam9_wdt.o
>>  obj-$(CONFIG_CADENCE_WATCHDOG) += cadence_wdt.o
>> diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
>> new file mode 100644
>> index 0000000..7ae45cc
>> --- /dev/null
>> +++ b/drivers/watchdog/sbsa_gwdt.c
>> @@ -0,0 +1,459 @@
>> +/*
>> + * SBSA(Server Base System Architecture) Generic Watchdog driver
>> + *
>> + * Copyright (c) 2015, Linaro Ltd.
>> + * Author: Fu Wei <fu.wei@linaro.org>
>> + *         Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License 2 as published
>> + * by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * The SBSA Generic watchdog driver is compatible with the pretimeout
>> + * concept of Linux kernel.
>> + * The timeout and pretimeout are determined by WCV or WOR.
>> + * The first watch period is set by writing WCV directly, that can
>> + * support more than 10s timeout at the maximum system counter
>> + * frequency (400MHz).
>> + * When WS0 is triggered, the second watch period (pretimeout) is
>> + * determined by one of these registers:
>> + * (1)WOR: 32bit register, this gives a maximum watch period of
>> + * around 10s at the maximum system counter frequency. It's loaded
>> + * automatically by hardware.
>> + * (2)WCV: If the pretimeout value is greater then "max_wor_timeout",
>> + * it will be loaded in WS0 interrupt routine. If system is in
>> + * ws0_mode (reboot by kexec/kdump in panic with watchdog enabled
>> + * and WS0 == true), the ping operation will only reload WCV.
>
> Below is the field comment about ws0_mode, it says ws0_mode is only
> for rebooting in second stage timeout, but kexec/kdump can reboot in
> either first or second stage

Great thanks for your feedback.

yes, if kexec/kdump reboot the system before the WS0, ws0_mode may not be set.
in this case, if WS0 is triggered during the reboot(AFAIK, panic will
disable irq, and in the early boot stage of system, irq is disabled,
too.), ws0_mode will be set at the next "open" in kdump kernel
if WS0 haven't triggered until the watchdog is opened again in kdump
kernel , ws0_mode won't  be set.

ws0_mode doesn't indicate if the system is in the kdump kernel, it
indicates that if WS0 is triggered, when the watchdog is initialized.

Do I answer your question?

>  * @ws0_mode:           indicate the system boot in the second stage timeout.
>
>
>> + * More details about the hardware specification of this device:
>> + * ARM DEN0029B - Server Base System Architecture (SBSA)
>> + *
>> + * Kernel/API:                         P------------------| pretimeout
>> + *               |----------------------------------------T timeout
>> + * SBSA GWDT:                          P---WOR (or WCV)---WS1 pretimeout
>> + *               |-------WCV----------WS0~~~(ws0_mode)~~~~T timeout
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/module.h>
>> +#include <linux/moduleparam.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/uaccess.h>
>> +#include <linux/watchdog.h>
>> +#include <asm/arch_timer.h>
>> +
>> +/* SBSA Generic Watchdog register definitions */
>> +/* refresh frame */
>> +#define SBSA_GWDT_WRR                                0x000
>> +
>> +/* control frame */
>> +#define SBSA_GWDT_WCS                                0x000
>> +#define SBSA_GWDT_WOR                                0x008
>> +#define SBSA_GWDT_WCV_LO                     0x010
>> +#define SBSA_GWDT_WCV_HI                     0x014
>> +
>> +/* refresh/control frame */
>> +#define SBSA_GWDT_W_IIDR                     0xfcc
>> +#define SBSA_GWDT_IDR                                0xfd0
>> +
>> +/* Watchdog Control and Status Register */
>> +#define SBSA_GWDT_WCS_EN                     BIT(0)
>> +#define SBSA_GWDT_WCS_WS0                    BIT(1)
>> +#define SBSA_GWDT_WCS_WS1                    BIT(2)
>> +
>> +/**
>> + * struct sbsa_gwdt - Internal representation of the SBSA GWDT
>> + * @wdd:             kernel watchdog_device structure
>> + * @clk:             store the System Counter clock frequency, in Hz.
>> + * @ws0_mode:                indicate the system boot in the second stage timeout.
>> + * @max_wor_timeout: the maximum timeout value for WOR (in seconds).
>> + * @refresh_base:    Virtual address of the watchdog refresh frame
>> + * @control_base:    Virtual address of the watchdog control frame
>> + */
>> +struct sbsa_gwdt {
>> +     struct watchdog_device  wdd;
>> +     u32                     clk;
>> +     bool                    ws0_mode;
>> +     int                     max_wor_timeout;
>> +     void __iomem            *refresh_base;
>> +     void __iomem            *control_base;
>> +};
>> +
>> +#define to_sbsa_gwdt(e) container_of(e, struct sbsa_gwdt, wdd)
>> +
>> +#define DEFAULT_TIMEOUT              30 /* seconds, the 1st + 2nd watch periods*/
>> +#define DEFAULT_PRETIMEOUT   10 /* seconds, the 2nd watch period*/
>> +
>> +static unsigned int timeout;
>> +module_param(timeout, uint, 0);
>> +MODULE_PARM_DESC(timeout,
>> +              "Watchdog timeout in seconds. (>=0, default="
>> +              __MODULE_STRING(DEFAULT_TIMEOUT) ")");
>> +
>> +static unsigned int pretimeout;
>> +module_param(pretimeout, uint, 0);
>> +MODULE_PARM_DESC(pretimeout,
>> +              "Watchdog pretimeout in seconds. (>=0, default="
>> +              __MODULE_STRING(DEFAULT_PRETIMEOUT) ")");
>> +
>> +static bool nowayout = WATCHDOG_NOWAYOUT;
>> +module_param(nowayout, bool, S_IRUGO);
>> +MODULE_PARM_DESC(nowayout,
>> +              "Watchdog cannot be stopped once started (default="
>> +              __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
>> +
>> +/*
>> + * help functions for accessing 64bit WCV register
>> + */
>> +static u64 sbsa_gwdt_get_wcv(struct watchdog_device *wdd)
>> +{
>> +     u32 wcv_lo, wcv_hi;
>> +     struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
>> +
>> +     do {
>> +             wcv_hi = readl_relaxed(gwdt->control_base + SBSA_GWDT_WCV_HI);
>> +             wcv_lo = readl_relaxed(gwdt->control_base + SBSA_GWDT_WCV_LO);
>> +     } while (wcv_hi != readl_relaxed(gwdt->control_base +
>> +                                      SBSA_GWDT_WCV_HI));
>> +
>> +     return (((u64)wcv_hi << 32) | wcv_lo);
>> +}
>> +
>> +static void sbsa_gwdt_set_wcv(struct watchdog_device *wdd, unsigned int t)
>> +{
>> +     struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
>> +     u64 wcv;
>> +
>> +     wcv = arch_counter_get_cntvct() + (u64)t * gwdt->clk;
>> +
>> +     writel_relaxed(upper_32_bits(wcv),
>> +                    gwdt->control_base + SBSA_GWDT_WCV_HI);
>> +     writel_relaxed(lower_32_bits(wcv),
>> +                    gwdt->control_base + SBSA_GWDT_WCV_LO);
>> +}
>> +
>> +/*
>> + * inline functions for reloading 64bit WCV register
>> + */
>> +static inline void reload_pretimeout_to_wcv(struct watchdog_device *wdd)
>> +{
>> +     sbsa_gwdt_set_wcv(wdd, wdd->pretimeout);
>> +}
>> +
>> +static inline void reload_first_stage_to_wcv(struct watchdog_device *wdd)
>> +{
>> +     sbsa_gwdt_set_wcv(wdd, wdd->timeout - wdd->pretimeout);
>> +}
>> +
>> +/*
>> + * watchdog operation functions
>> + */
>> +static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
>> +                              unsigned int timeout)
>> +{
>> +     wdd->timeout = timeout;
>> +
>> +     return 0;
>> +}
>> +
>> +static int sbsa_gwdt_set_pretimeout(struct watchdog_device *wdd,
>> +                                 unsigned int pretimeout)
>> +{
>> +     struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
>> +     u32 wor;
>> +
>> +     wdd->pretimeout = pretimeout;
>> +
>> +     /* If ws0_mode == true, we won't touch WOR */
>> +     if (!gwdt->ws0_mode) {
>> +             if (!pretimeout)
>> +                     /*
>> +                      * If pretimeout is 0, it gives driver a timeslot (1s)
>> +                      * to update WCV after an explicit refresh
>> +                      * (sbsa_gwdt_start)
>> +                      */
>> +                     wor = gwdt->clk;
>> +             else
>> +                     if (pretimeout > gwdt->max_wor_timeout)
>> +                             wor = U32_MAX;
>> +                     else
>> +                             wor = pretimeout * gwdt->clk;
>> +
>> +             /* wtite WOR, that will cause an explicit watchdog refresh */
>> +             writel_relaxed(wor, gwdt->control_base + SBSA_GWDT_WOR);
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
>> +{
>> +     struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
>> +     u64 timeleft = sbsa_gwdt_get_wcv(wdd) - arch_counter_get_cntvct();
>> +
>> +     do_div(timeleft, gwdt->clk);
>> +
>> +     return timeleft;
>> +}
>> +
>> +static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
>> +{
>> +     struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
>> +
>> +     if (gwdt->ws0_mode)
>> +             reload_pretimeout_to_wcv(wdd);
>> +     else
>> +             reload_first_stage_to_wcv(wdd);
>> +
>> +     return 0;
>> +}
>> +
>> +static int sbsa_gwdt_start(struct watchdog_device *wdd)
>> +{
>> +     struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
>> +
>> +     /* If ws0_mode == true, the watchdog is enabled */
>> +     if (!gwdt->ws0_mode)
>> +             /* writing WCS will cause an explicit watchdog refresh */
>> +             writel_relaxed(SBSA_GWDT_WCS_EN,
>> +                            gwdt->control_base + SBSA_GWDT_WCS);
>> +
>> +     return sbsa_gwdt_keepalive(wdd);
>> +}
>> +
>> +static int sbsa_gwdt_stop(struct watchdog_device *wdd)
>> +{
>> +     struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
>> +
>> +     writel_relaxed(0, gwdt->control_base + SBSA_GWDT_WCS);
>> +     /*
>> +      * Writing WCS has caused an explicit watchdog refresh.
>> +      * Both watchdog signals are deasserted, so clean ws0_mode flag.
>> +      */
>> +     gwdt->ws0_mode = false;
>> +
>> +     return 0;
>> +}
>> +
>> +static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
>> +{
>> +     struct sbsa_gwdt *gwdt = (struct sbsa_gwdt *)dev_id;
>> +     struct watchdog_device *wdd = &gwdt->wdd;
>> +
>> +     /* We don't use pretimeout, trigger WS1 now */
>> +     if (!wdd->pretimeout)
>> +             sbsa_gwdt_set_wcv(wdd, 0);
>> +
>> +     /*
>> +      * The pretimeout is valid, go panic
>> +      * If pretimeout is greater then "max_wor_timeout",
>> +      * reload the right value to WCV, then panic
>> +      */
>> +     if (wdd->pretimeout > gwdt->max_wor_timeout)
>> +             reload_pretimeout_to_wcv(wdd);
>> +     panic("SBSA Watchdog pre-timeout");
>> +
>> +     return IRQ_HANDLED;
>> +}
>> +
>> +static struct watchdog_info sbsa_gwdt_info = {
>> +     .identity       = "SBSA Generic Watchdog",
>> +     .options        = WDIOF_SETTIMEOUT |
>> +                       WDIOF_KEEPALIVEPING |
>> +                       WDIOF_MAGICCLOSE |
>> +                       WDIOF_PRETIMEOUT |
>> +                       WDIOF_CARDRESET,
>> +};
>> +
>> +static struct watchdog_ops sbsa_gwdt_ops = {
>> +     .owner          = THIS_MODULE,
>> +     .start          = sbsa_gwdt_start,
>> +     .stop           = sbsa_gwdt_stop,
>> +     .ping           = sbsa_gwdt_keepalive,
>> +     .set_timeout    = sbsa_gwdt_set_timeout,
>> +     .set_pretimeout = sbsa_gwdt_set_pretimeout,
>> +     .get_timeleft   = sbsa_gwdt_get_timeleft,
>> +};
>> +
>> +static int sbsa_gwdt_probe(struct platform_device *pdev)
>> +{
>> +     void __iomem *rf_base, *cf_base;
>> +     struct device *dev = &pdev->dev;
>> +     struct watchdog_device *wdd;
>> +     struct sbsa_gwdt *gwdt;
>> +     struct resource *res;
>> +     int ret, irq;
>> +     u32 status;
>> +
>> +     gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
>> +     if (!gwdt)
>> +             return -ENOMEM;
>> +     platform_set_drvdata(pdev, gwdt);
>> +
>> +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +     cf_base = devm_ioremap_resource(dev, res);
>> +     if (IS_ERR(cf_base))
>> +             return PTR_ERR(cf_base);
>> +
>> +     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> +     rf_base = devm_ioremap_resource(dev, res);
>> +     if (IS_ERR(rf_base))
>> +             return PTR_ERR(rf_base);
>> +
>> +     irq = platform_get_irq(pdev, 0);
>> +     if (irq < 0) {
>> +             dev_err(dev, "unable to get ws0 interrupt.\n");
>> +             return irq;
>> +     }
>> +
>> +     /*
>> +      * Get the frequency of system counter from the cp15 interface of ARM
>> +      * Generic timer. We don't need to check it, because if it returns "0",
>> +      * system would panic in very early stage.
>> +      */
>> +     gwdt->clk = arch_timer_get_cntfrq();
>> +     gwdt->refresh_base = rf_base;
>> +     gwdt->control_base = cf_base;
>> +     gwdt->max_wor_timeout = U32_MAX / gwdt->clk;
>> +     gwdt->ws0_mode = false;
>> +
>> +     wdd = &gwdt->wdd;
>> +     wdd->parent = dev;
>> +     wdd->info = &sbsa_gwdt_info;
>> +     wdd->ops = &sbsa_gwdt_ops;
>> +     watchdog_set_drvdata(wdd, gwdt);
>> +     watchdog_set_nowayout(wdd, nowayout);
>> +
>> +     wdd->min_pretimeout = 0;
>> +     wdd->min_timeout = 1;
>> +
>> +     /*
>> +      * Because the maximum of gwdt->clk is 400MHz and the maximum of WCV is
>> +      * U64_MAX, so the result of (U64_MAX / gwdt->clk) is always greater
>> +      * than U32_MAX. And the maximum of "unsigned int" is U32_MAX on ARM64.
>> +      * So we set the maximum value of pretimeout and timeout below.
>> +      */
>> +     wdd->max_pretimeout = U32_MAX - 1;
>> +     wdd->max_timeout = U32_MAX;
>> +
>> +     wdd->pretimeout = DEFAULT_PRETIMEOUT;
>> +     wdd->timeout = DEFAULT_TIMEOUT;
>> +     watchdog_init_timeouts(wdd, pretimeout, timeout, dev);
>> +
>> +     status = readl_relaxed(gwdt->control_base + SBSA_GWDT_WCS);
>> +     if (status & SBSA_GWDT_WCS_WS1) {
>> +             dev_warn(dev, "System reset by WDT.\n");
>> +             wdd->bootstatus |= WDIOF_CARDRESET;
>> +     } else if (status == (SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_EN)) {
>> +             gwdt->ws0_mode = true;
>> +     }
>> +
>> +     ret = devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0,
>> +                            pdev->name, gwdt);
>> +     if (ret) {
>> +             dev_err(dev, "unable to request IRQ %d\n", irq);
>> +             return ret;
>> +     }
>> +
>> +     ret = watchdog_register_device(wdd);
>> +     if (ret)
>> +             return ret;
>> +
>> +     /* If ws0_mode == true, the line won't update WOR */
>> +     sbsa_gwdt_set_pretimeout(wdd, wdd->pretimeout);
>> +
>> +     /*
>> +      * If watchdog is already enabled, do a ping operation
>> +      * to keep system running
>> +      */
>> +     if (status & SBSA_GWDT_WCS_EN)
>> +             sbsa_gwdt_keepalive(wdd);
>> +
>> +     dev_info(dev, "Initialized with %ds timeout, %ds pretimeout @ %u Hz%s\n",
>> +              wdd->timeout, wdd->pretimeout, gwdt->clk,
>> +              status & SBSA_GWDT_WCS_EN ?
>> +                     gwdt->ws0_mode ? " [second stage]" : " [enabled]" :
>> +                     "");
>> +
>> +     return 0;
>> +}
>> +
>> +static void sbsa_gwdt_shutdown(struct platform_device *pdev)
>> +{
>> +     struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev);
>> +
>> +     sbsa_gwdt_stop(&gwdt->wdd);
>> +}
>> +
>> +static int sbsa_gwdt_remove(struct platform_device *pdev)
>> +{
>> +     struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev);
>> +
>> +     watchdog_unregister_device(&gwdt->wdd);
>> +
>> +     return 0;
>> +}
>> +
>> +/* Disable watchdog if it is active during suspend */
>> +static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
>> +{
>> +     struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
>> +
>> +     if (watchdog_active(&gwdt->wdd))
>> +             sbsa_gwdt_stop(&gwdt->wdd);
>> +
>> +     return 0;
>> +}
>> +
>> +/* Enable watchdog and configure it if necessary */
>> +static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
>> +{
>> +     struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
>> +
>> +     if (watchdog_active(&gwdt->wdd))
>> +             sbsa_gwdt_start(&gwdt->wdd);
>> +
>> +     return 0;
>> +}
>> +
>> +static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
>> +     SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
>> +};
>> +
>> +static const struct of_device_id sbsa_gwdt_of_match[] = {
>> +     { .compatible = "arm,sbsa-gwdt", },
>> +     {},
>> +};
>> +MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);
>> +
>> +static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
>> +     { .name = "sbsa-gwdt", },
>> +     {},
>> +};
>> +MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);
>> +
>> +static struct platform_driver sbsa_gwdt_driver = {
>> +     .driver = {
>> +             .name = "sbsa-gwdt",
>> +             .pm = &sbsa_gwdt_pm_ops,
>> +             .of_match_table = sbsa_gwdt_of_match,
>> +     },
>> +     .probe = sbsa_gwdt_probe,
>> +     .remove = sbsa_gwdt_remove,
>> +     .shutdown = sbsa_gwdt_shutdown,
>> +     .id_table = sbsa_gwdt_pdev_match,
>> +};
>> +
>> +module_platform_driver(sbsa_gwdt_driver);
>> +
>> +MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
>> +MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
>> +MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 2.4.3
>>
Dave Young Sept. 16, 2015, 1:57 a.m. | #7
> >> diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
> >> new file mode 100644
> >> index 0000000..7ae45cc
> >> --- /dev/null
> >> +++ b/drivers/watchdog/sbsa_gwdt.c
> >> @@ -0,0 +1,459 @@
> >> +/*
> >> + * SBSA(Server Base System Architecture) Generic Watchdog driver
> >> + *
> >> + * Copyright (c) 2015, Linaro Ltd.
> >> + * Author: Fu Wei <fu.wei@linaro.org>
> >> + *         Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License 2 as published
> >> + * by the Free Software Foundation.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >> + * GNU General Public License for more details.
> >> + *
> >> + * The SBSA Generic watchdog driver is compatible with the pretimeout
> >> + * concept of Linux kernel.
> >> + * The timeout and pretimeout are determined by WCV or WOR.
> >> + * The first watch period is set by writing WCV directly, that can
> >> + * support more than 10s timeout at the maximum system counter
> >> + * frequency (400MHz).
> >> + * When WS0 is triggered, the second watch period (pretimeout) is
> >> + * determined by one of these registers:
> >> + * (1)WOR: 32bit register, this gives a maximum watch period of
> >> + * around 10s at the maximum system counter frequency. It's loaded
> >> + * automatically by hardware.
> >> + * (2)WCV: If the pretimeout value is greater then "max_wor_timeout",
> >> + * it will be loaded in WS0 interrupt routine. If system is in
> >> + * ws0_mode (reboot by kexec/kdump in panic with watchdog enabled
> >> + * and WS0 == true), the ping operation will only reload WCV.
> >
> > Below is the field comment about ws0_mode, it says ws0_mode is only
> > for rebooting in second stage timeout, but kexec/kdump can reboot in
> > either first or second stage
> 
> Great thanks for your feedback.
> 
> yes, if kexec/kdump reboot the system before the WS0, ws0_mode may not be set.
> in this case, if WS0 is triggered during the reboot(AFAIK, panic will
> disable irq, and in the early boot stage of system, irq is disabled,
> too.), ws0_mode will be set at the next "open" in kdump kernel
> if WS0 haven't triggered until the watchdog is opened again in kdump
> kernel , ws0_mode won't  be set.
> 
> ws0_mode doesn't indicate if the system is in the kdump kernel, it
> indicates that if WS0 is triggered, when the watchdog is initialized.
> 
> Do I answer your question?

Yes, thanks for explanation. So it sounds better to change the comment like below?
from
(reboot by kexec/kdump in panic with watchdog enabled and WS0 == true)
to
(reboot in the pre-timeout stage and WS0 == true)

Thanks
Dave
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Fu Wei Oct. 13, 2015, 8:34 a.m. | #8
Hi Dave,

On 16 September 2015 at 09:57, Dave Young <dyoung@redhat.com> wrote:
>> >> diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
>> >> new file mode 100644
>> >> index 0000000..7ae45cc
>> >> --- /dev/null
>> >> +++ b/drivers/watchdog/sbsa_gwdt.c
>> >> @@ -0,0 +1,459 @@
>> >> +/*
>> >> + * SBSA(Server Base System Architecture) Generic Watchdog driver
>> >> + *
>> >> + * Copyright (c) 2015, Linaro Ltd.
>> >> + * Author: Fu Wei <fu.wei@linaro.org>
>> >> + *         Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or modify
>> >> + * it under the terms of the GNU General Public License 2 as published
>> >> + * by the Free Software Foundation.
>> >> + *
>> >> + * This program is distributed in the hope that it will be useful,
>> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> >> + * GNU General Public License for more details.
>> >> + *
>> >> + * The SBSA Generic watchdog driver is compatible with the pretimeout
>> >> + * concept of Linux kernel.
>> >> + * The timeout and pretimeout are determined by WCV or WOR.
>> >> + * The first watch period is set by writing WCV directly, that can
>> >> + * support more than 10s timeout at the maximum system counter
>> >> + * frequency (400MHz).
>> >> + * When WS0 is triggered, the second watch period (pretimeout) is
>> >> + * determined by one of these registers:
>> >> + * (1)WOR: 32bit register, this gives a maximum watch period of
>> >> + * around 10s at the maximum system counter frequency. It's loaded
>> >> + * automatically by hardware.
>> >> + * (2)WCV: If the pretimeout value is greater then "max_wor_timeout",
>> >> + * it will be loaded in WS0 interrupt routine. If system is in
>> >> + * ws0_mode (reboot by kexec/kdump in panic with watchdog enabled
>> >> + * and WS0 == true), the ping operation will only reload WCV.
>> >
>> > Below is the field comment about ws0_mode, it says ws0_mode is only
>> > for rebooting in second stage timeout, but kexec/kdump can reboot in
>> > either first or second stage
>>
>> Great thanks for your feedback.
>>
>> yes, if kexec/kdump reboot the system before the WS0, ws0_mode may not be set.
>> in this case, if WS0 is triggered during the reboot(AFAIK, panic will
>> disable irq, and in the early boot stage of system, irq is disabled,
>> too.), ws0_mode will be set at the next "open" in kdump kernel
>> if WS0 haven't triggered until the watchdog is opened again in kdump
>> kernel , ws0_mode won't  be set.
>>
>> ws0_mode doesn't indicate if the system is in the kdump kernel, it
>> indicates that if WS0 is triggered, when the watchdog is initialized.
>>
>> Do I answer your question?
>
> Yes, thanks for explanation. So it sounds better to change the comment like below?
> from
> (reboot by kexec/kdump in panic with watchdog enabled and WS0 == true)
> to
> (reboot in the pre-timeout stage and WS0 == true)

" in the pre-timeout stage" means " WS0 == true", so I think we should say:
(reboot with watchdog enabled and WS0 == true)

Thanks for your suggestion.

>
> Thanks
> Dave

Patch

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 241fafd..b2734f0 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -173,6 +173,20 @@  config ARM_SP805_WATCHDOG
 	  ARM Primecell SP805 Watchdog timer. This will reboot your system when
 	  the timeout is reached.
 
+config ARM_SBSA_WATCHDOG
+	tristate "ARM SBSA Generic Watchdog"
+	depends on ARM64
+	depends on ARM_ARCH_TIMER
+	select WATCHDOG_CORE
+	help
+	  ARM SBSA Generic Watchdog. This watchdog has two Watchdog timeouts.
+	  The first timeout will trigger a panic; the second timeout will
+	  trigger a system reset.
+	  More details: ARM DEN0029B - Server Base System Architecture (SBSA)
+
+	  To compile this driver as module, choose M here: The module
+	  will be called sbsa_gwdt.
+
 config AT91RM9200_WATCHDOG
 	tristate "AT91RM9200 watchdog"
 	depends on SOC_AT91RM9200 && MFD_SYSCON
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 59ea9a1..be8e7c5 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -30,6 +30,7 @@  obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
 
 # ARM Architecture
 obj-$(CONFIG_ARM_SP805_WATCHDOG) += sp805_wdt.o
+obj-$(CONFIG_ARM_SBSA_WATCHDOG) += sbsa_gwdt.o
 obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
 obj-$(CONFIG_AT91SAM9X_WATCHDOG) += at91sam9_wdt.o
 obj-$(CONFIG_CADENCE_WATCHDOG) += cadence_wdt.o
diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
new file mode 100644
index 0000000..7ae45cc
--- /dev/null
+++ b/drivers/watchdog/sbsa_gwdt.c
@@ -0,0 +1,459 @@ 
+/*
+ * SBSA(Server Base System Architecture) Generic Watchdog driver
+ *
+ * Copyright (c) 2015, Linaro Ltd.
+ * Author: Fu Wei <fu.wei@linaro.org>
+ *         Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * The SBSA Generic watchdog driver is compatible with the pretimeout
+ * concept of Linux kernel.
+ * The timeout and pretimeout are determined by WCV or WOR.
+ * The first watch period is set by writing WCV directly, that can
+ * support more than 10s timeout at the maximum system counter
+ * frequency (400MHz).
+ * When WS0 is triggered, the second watch period (pretimeout) is
+ * determined by one of these registers:
+ * (1)WOR: 32bit register, this gives a maximum watch period of
+ * around 10s at the maximum system counter frequency. It's loaded
+ * automatically by hardware.
+ * (2)WCV: If the pretimeout value is greater then "max_wor_timeout",
+ * it will be loaded in WS0 interrupt routine. If system is in
+ * ws0_mode (reboot by kexec/kdump in panic with watchdog enabled
+ * and WS0 == true), the ping operation will only reload WCV.
+ * More details about the hardware specification of this device:
+ * ARM DEN0029B - Server Base System Architecture (SBSA)
+ *
+ * Kernel/API:                         P------------------| pretimeout
+ *               |----------------------------------------T timeout
+ * SBSA GWDT:                          P---WOR (or WCV)---WS1 pretimeout
+ *               |-------WCV----------WS0~~~(ws0_mode)~~~~T timeout
+ */
+
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/watchdog.h>
+#include <asm/arch_timer.h>
+
+/* SBSA Generic Watchdog register definitions */
+/* refresh frame */
+#define SBSA_GWDT_WRR				0x000
+
+/* control frame */
+#define SBSA_GWDT_WCS				0x000
+#define SBSA_GWDT_WOR				0x008
+#define SBSA_GWDT_WCV_LO			0x010
+#define SBSA_GWDT_WCV_HI			0x014
+
+/* refresh/control frame */
+#define SBSA_GWDT_W_IIDR			0xfcc
+#define SBSA_GWDT_IDR				0xfd0
+
+/* Watchdog Control and Status Register */
+#define SBSA_GWDT_WCS_EN			BIT(0)
+#define SBSA_GWDT_WCS_WS0			BIT(1)
+#define SBSA_GWDT_WCS_WS1			BIT(2)
+
+/**
+ * struct sbsa_gwdt - Internal representation of the SBSA GWDT
+ * @wdd:		kernel watchdog_device structure
+ * @clk:		store the System Counter clock frequency, in Hz.
+ * @ws0_mode:		indicate the system boot in the second stage timeout.
+ * @max_wor_timeout:	the maximum timeout value for WOR (in seconds).
+ * @refresh_base:	Virtual address of the watchdog refresh frame
+ * @control_base:	Virtual address of the watchdog control frame
+ */
+struct sbsa_gwdt {
+	struct watchdog_device	wdd;
+	u32			clk;
+	bool			ws0_mode;
+	int			max_wor_timeout;
+	void __iomem		*refresh_base;
+	void __iomem		*control_base;
+};
+
+#define to_sbsa_gwdt(e) container_of(e, struct sbsa_gwdt, wdd)
+
+#define DEFAULT_TIMEOUT		30 /* seconds, the 1st + 2nd watch periods*/
+#define DEFAULT_PRETIMEOUT	10 /* seconds, the 2nd watch period*/
+
+static unsigned int timeout;
+module_param(timeout, uint, 0);
+MODULE_PARM_DESC(timeout,
+		 "Watchdog timeout in seconds. (>=0, default="
+		 __MODULE_STRING(DEFAULT_TIMEOUT) ")");
+
+static unsigned int pretimeout;
+module_param(pretimeout, uint, 0);
+MODULE_PARM_DESC(pretimeout,
+		 "Watchdog pretimeout in seconds. (>=0, default="
+		 __MODULE_STRING(DEFAULT_PRETIMEOUT) ")");
+
+static bool nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, bool, S_IRUGO);
+MODULE_PARM_DESC(nowayout,
+		 "Watchdog cannot be stopped once started (default="
+		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+/*
+ * help functions for accessing 64bit WCV register
+ */
+static u64 sbsa_gwdt_get_wcv(struct watchdog_device *wdd)
+{
+	u32 wcv_lo, wcv_hi;
+	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
+
+	do {
+		wcv_hi = readl_relaxed(gwdt->control_base + SBSA_GWDT_WCV_HI);
+		wcv_lo = readl_relaxed(gwdt->control_base + SBSA_GWDT_WCV_LO);
+	} while (wcv_hi != readl_relaxed(gwdt->control_base +
+					 SBSA_GWDT_WCV_HI));
+
+	return (((u64)wcv_hi << 32) | wcv_lo);
+}
+
+static void sbsa_gwdt_set_wcv(struct watchdog_device *wdd, unsigned int t)
+{
+	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
+	u64 wcv;
+
+	wcv = arch_counter_get_cntvct() + (u64)t * gwdt->clk;
+
+	writel_relaxed(upper_32_bits(wcv),
+		       gwdt->control_base + SBSA_GWDT_WCV_HI);
+	writel_relaxed(lower_32_bits(wcv),
+		       gwdt->control_base + SBSA_GWDT_WCV_LO);
+}
+
+/*
+ * inline functions for reloading 64bit WCV register
+ */
+static inline void reload_pretimeout_to_wcv(struct watchdog_device *wdd)
+{
+	sbsa_gwdt_set_wcv(wdd, wdd->pretimeout);
+}
+
+static inline void reload_first_stage_to_wcv(struct watchdog_device *wdd)
+{
+	sbsa_gwdt_set_wcv(wdd, wdd->timeout - wdd->pretimeout);
+}
+
+/*
+ * watchdog operation functions
+ */
+static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
+				 unsigned int timeout)
+{
+	wdd->timeout = timeout;
+
+	return 0;
+}
+
+static int sbsa_gwdt_set_pretimeout(struct watchdog_device *wdd,
+				    unsigned int pretimeout)
+{
+	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
+	u32 wor;
+
+	wdd->pretimeout = pretimeout;
+
+	/* If ws0_mode == true, we won't touch WOR */
+	if (!gwdt->ws0_mode) {
+		if (!pretimeout)
+			/*
+			 * If pretimeout is 0, it gives driver a timeslot (1s)
+			 * to update WCV after an explicit refresh
+			 * (sbsa_gwdt_start)
+			 */
+			wor = gwdt->clk;
+		else
+			if (pretimeout > gwdt->max_wor_timeout)
+				wor = U32_MAX;
+			else
+				wor = pretimeout * gwdt->clk;
+
+		/* wtite WOR, that will cause an explicit watchdog refresh */
+		writel_relaxed(wor, gwdt->control_base + SBSA_GWDT_WOR);
+	}
+
+	return 0;
+}
+
+static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
+{
+	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
+	u64 timeleft = sbsa_gwdt_get_wcv(wdd) - arch_counter_get_cntvct();
+
+	do_div(timeleft, gwdt->clk);
+
+	return timeleft;
+}
+
+static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
+{
+	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
+
+	if (gwdt->ws0_mode)
+		reload_pretimeout_to_wcv(wdd);
+	else
+		reload_first_stage_to_wcv(wdd);
+
+	return 0;
+}
+
+static int sbsa_gwdt_start(struct watchdog_device *wdd)
+{
+	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
+
+	/* If ws0_mode == true, the watchdog is enabled */
+	if (!gwdt->ws0_mode)
+		/* writing WCS will cause an explicit watchdog refresh */
+		writel_relaxed(SBSA_GWDT_WCS_EN,
+			       gwdt->control_base + SBSA_GWDT_WCS);
+
+	return sbsa_gwdt_keepalive(wdd);
+}
+
+static int sbsa_gwdt_stop(struct watchdog_device *wdd)
+{
+	struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);
+
+	writel_relaxed(0, gwdt->control_base + SBSA_GWDT_WCS);
+	/*
+	 * Writing WCS has caused an explicit watchdog refresh.
+	 * Both watchdog signals are deasserted, so clean ws0_mode flag.
+	 */
+	gwdt->ws0_mode = false;
+
+	return 0;
+}
+
+static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
+{
+	struct sbsa_gwdt *gwdt = (struct sbsa_gwdt *)dev_id;
+	struct watchdog_device *wdd = &gwdt->wdd;
+
+	/* We don't use pretimeout, trigger WS1 now */
+	if (!wdd->pretimeout)
+		sbsa_gwdt_set_wcv(wdd, 0);
+
+	/*
+	 * The pretimeout is valid, go panic
+	 * If pretimeout is greater then "max_wor_timeout",
+	 * reload the right value to WCV, then panic
+	 */
+	if (wdd->pretimeout > gwdt->max_wor_timeout)
+		reload_pretimeout_to_wcv(wdd);
+	panic("SBSA Watchdog pre-timeout");
+
+	return IRQ_HANDLED;
+}
+
+static struct watchdog_info sbsa_gwdt_info = {
+	.identity	= "SBSA Generic Watchdog",
+	.options	= WDIOF_SETTIMEOUT |
+			  WDIOF_KEEPALIVEPING |
+			  WDIOF_MAGICCLOSE |
+			  WDIOF_PRETIMEOUT |
+			  WDIOF_CARDRESET,
+};
+
+static struct watchdog_ops sbsa_gwdt_ops = {
+	.owner		= THIS_MODULE,
+	.start		= sbsa_gwdt_start,
+	.stop		= sbsa_gwdt_stop,
+	.ping		= sbsa_gwdt_keepalive,
+	.set_timeout	= sbsa_gwdt_set_timeout,
+	.set_pretimeout	= sbsa_gwdt_set_pretimeout,
+	.get_timeleft	= sbsa_gwdt_get_timeleft,
+};
+
+static int sbsa_gwdt_probe(struct platform_device *pdev)
+{
+	void __iomem *rf_base, *cf_base;
+	struct device *dev = &pdev->dev;
+	struct watchdog_device *wdd;
+	struct sbsa_gwdt *gwdt;
+	struct resource *res;
+	int ret, irq;
+	u32 status;
+
+	gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
+	if (!gwdt)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, gwdt);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	cf_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(cf_base))
+		return PTR_ERR(cf_base);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	rf_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(rf_base))
+		return PTR_ERR(rf_base);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(dev, "unable to get ws0 interrupt.\n");
+		return irq;
+	}
+
+	/*
+	 * Get the frequency of system counter from the cp15 interface of ARM
+	 * Generic timer. We don't need to check it, because if it returns "0",
+	 * system would panic in very early stage.
+	 */
+	gwdt->clk = arch_timer_get_cntfrq();
+	gwdt->refresh_base = rf_base;
+	gwdt->control_base = cf_base;
+	gwdt->max_wor_timeout = U32_MAX / gwdt->clk;
+	gwdt->ws0_mode = false;
+
+	wdd = &gwdt->wdd;
+	wdd->parent = dev;
+	wdd->info = &sbsa_gwdt_info;
+	wdd->ops = &sbsa_gwdt_ops;
+	watchdog_set_drvdata(wdd, gwdt);
+	watchdog_set_nowayout(wdd, nowayout);
+
+	wdd->min_pretimeout = 0;
+	wdd->min_timeout = 1;
+
+	/*
+	 * Because the maximum of gwdt->clk is 400MHz and the maximum of WCV is
+	 * U64_MAX, so the result of (U64_MAX / gwdt->clk) is always greater
+	 * than U32_MAX. And the maximum of "unsigned int" is U32_MAX on ARM64.
+	 * So we set the maximum value of pretimeout and timeout below.
+	 */
+	wdd->max_pretimeout = U32_MAX - 1;
+	wdd->max_timeout = U32_MAX;
+
+	wdd->pretimeout = DEFAULT_PRETIMEOUT;
+	wdd->timeout = DEFAULT_TIMEOUT;
+	watchdog_init_timeouts(wdd, pretimeout, timeout, dev);
+
+	status = readl_relaxed(gwdt->control_base + SBSA_GWDT_WCS);
+	if (status & SBSA_GWDT_WCS_WS1) {
+		dev_warn(dev, "System reset by WDT.\n");
+		wdd->bootstatus |= WDIOF_CARDRESET;
+	} else if (status == (SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_EN)) {
+		gwdt->ws0_mode = true;
+	}
+
+	ret = devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0,
+			       pdev->name, gwdt);
+	if (ret) {
+		dev_err(dev, "unable to request IRQ %d\n", irq);
+		return ret;
+	}
+
+	ret = watchdog_register_device(wdd);
+	if (ret)
+		return ret;
+
+	/* If ws0_mode == true, the line won't update WOR */
+	sbsa_gwdt_set_pretimeout(wdd, wdd->pretimeout);
+
+	/*
+	 * If watchdog is already enabled, do a ping operation
+	 * to keep system running
+	 */
+	if (status & SBSA_GWDT_WCS_EN)
+		sbsa_gwdt_keepalive(wdd);
+
+	dev_info(dev, "Initialized with %ds timeout, %ds pretimeout @ %u Hz%s\n",
+		 wdd->timeout, wdd->pretimeout, gwdt->clk,
+		 status & SBSA_GWDT_WCS_EN ?
+			gwdt->ws0_mode ? " [second stage]" : " [enabled]" :
+			"");
+
+	return 0;
+}
+
+static void sbsa_gwdt_shutdown(struct platform_device *pdev)
+{
+	struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev);
+
+	sbsa_gwdt_stop(&gwdt->wdd);
+}
+
+static int sbsa_gwdt_remove(struct platform_device *pdev)
+{
+	struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev);
+
+	watchdog_unregister_device(&gwdt->wdd);
+
+	return 0;
+}
+
+/* Disable watchdog if it is active during suspend */
+static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
+{
+	struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
+
+	if (watchdog_active(&gwdt->wdd))
+		sbsa_gwdt_stop(&gwdt->wdd);
+
+	return 0;
+}
+
+/* Enable watchdog and configure it if necessary */
+static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
+{
+	struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
+
+	if (watchdog_active(&gwdt->wdd))
+		sbsa_gwdt_start(&gwdt->wdd);
+
+	return 0;
+}
+
+static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
+};
+
+static const struct of_device_id sbsa_gwdt_of_match[] = {
+	{ .compatible = "arm,sbsa-gwdt", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);
+
+static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
+	{ .name = "sbsa-gwdt", },
+	{},
+};
+MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);
+
+static struct platform_driver sbsa_gwdt_driver = {
+	.driver = {
+		.name = "sbsa-gwdt",
+		.pm = &sbsa_gwdt_pm_ops,
+		.of_match_table = sbsa_gwdt_of_match,
+	},
+	.probe = sbsa_gwdt_probe,
+	.remove = sbsa_gwdt_remove,
+	.shutdown = sbsa_gwdt_shutdown,
+	.id_table = sbsa_gwdt_pdev_match,
+};
+
+module_platform_driver(sbsa_gwdt_driver);
+
+MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
+MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
+MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
+MODULE_LICENSE("GPL v2");