| Message ID | 20211221174844.56385-5-miquel.raynal@bootlin.com |
|---|---|
| State | New |
| Headers | show |
| Series | External ECC engines & Macronix support | expand |
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 101cc71bffa7..98e0cc4236e3 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1388,10 +1388,15 @@ static const char *cqspi_get_name(struct spi_mem *mem) return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); } +static const struct spi_controller_mem_caps cqspi_mem_caps = { + .dtr = true, +}; + static const struct spi_controller_mem_ops cqspi_mem_ops = { .exec_op = cqspi_exec_mem_op, .get_name = cqspi_get_name, .supports_op = cqspi_supports_mem_op, + .caps = &cqspi_mem_caps, }; static int cqspi_setup_flash(struct cqspi_st *cqspi)
This controller has DTR support, so advertize it with a capability now that the spi_controller_mem_ops structure contains this new field. This will later be used by the core to discriminate whether an operation is supported or not, in a more generic way than having different helpers. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/spi/spi-cadence-quadspi.c | 5 +++++ 1 file changed, 5 insertions(+)