@@ -1155,6 +1155,7 @@ static void spinand_mtd_resume(struct mtd_info *mtd)
struct spinand_device *spinand = mtd_to_spinand(mtd);
int ret;
+ spinand->protocol = SPINAND_1S_1S_1S;
ret = spinand_reset_op(spinand);
if (ret)
return;
@@ -1181,6 +1182,7 @@ static int spinand_init(struct spinand_device *spinand)
if (!spinand->scratchbuf)
return -ENOMEM;
+ spinand->protocol = SPINAND_1S_1S_1S;
ret = spinand_detect(spinand);
if (ret)
goto err_free_bufs;
@@ -194,6 +194,18 @@
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_DATA_OUT_DTR(len, buf, 8))
+/**
+ * enum spinand_protocol - List of SPI protocols to denote the op protocol and
+ * SPI NAND flash IO modes.
+ */
+enum spinand_protocol {
+ SPINAND_1S_1S_1S,
+ SPINAND_2S_2S_2S,
+ SPINAND_4S_4S_4S,
+ SPINAND_8S_8S_8S,
+ SPINAND_8D_8D_8D,
+};
+
/**
* Standard SPI NAND flash commands
*/
@@ -461,6 +473,8 @@ struct spinand_dirmap {
* this die. Only required if your chip exposes several dies
* @cur_target: currently selected target/die
* @eccinfo: on-die ECC information
+ * @protocol: SPI IO protocol in operation. Update on successful transition into
+ * a different SPI IO protocol.
* @cfg_cache: config register cache. One entry per die
* @databuf: bounce buffer for data
* @oobbuf: bounce buffer for OOB data
@@ -492,6 +506,8 @@ struct spinand_device {
struct spinand_ecc_info eccinfo;
+ enum spinand_protocol protocol;
+
u8 *cfg_cache;
u8 *databuf;
u8 *oobbuf;
Unlike Dual and Quad SPI modes flashes, Octal DTR SPI NAND flashes require all instructions to be made in 8D-8D-8D protocol when the flash is in Octal DTR mode. Hence, storing the current SPI IO mode becomes necessary for operating the flash and switching between modes. Store the current SPI IO mode in the spinand struct using a spinand_protocol enum. This would act as a flag, denoting that the core should use the given SPI protocol all types of flash operations. Signed-off-by: Apurva Nandan <a-nandan@ti.com> --- drivers/mtd/nand/spi/core.c | 2 ++ include/linux/mtd/spinand.h | 16 ++++++++++++++++ 2 files changed, 18 insertions(+)