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[209.85.215.44]) by mx.google.com with ESMTPS id zc4si6604942lbb.83.2015.09.18.09.28.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Sep 2015 09:28:10 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) client-ip=209.85.215.44; Received: by lamp12 with SMTP id p12so33023922lam.0 for ; Fri, 18 Sep 2015 09:28:10 -0700 (PDT) X-Received: by 10.152.23.199 with SMTP id o7mr3175323laf.76.1442593690095; Fri, 18 Sep 2015 09:28:10 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp401891lbq; Fri, 18 Sep 2015 09:28:09 -0700 (PDT) X-Received: by 10.50.80.10 with SMTP id n10mr264607igx.54.1442593688860; Fri, 18 Sep 2015 09:28:08 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id im6si7536656igb.0.2015.09.18.09.28.08; Fri, 18 Sep 2015 09:28:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754972AbbIRQ2A (ORCPT + 30 others); Fri, 18 Sep 2015 12:28:00 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:34965 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754827AbbIRQ13 (ORCPT ); Fri, 18 Sep 2015 12:27:29 -0400 Received: by pacfv12 with SMTP id fv12so56045441pac.2 for ; Fri, 18 Sep 2015 09:27:28 -0700 (PDT) X-Received: by 10.68.230.33 with SMTP id sv1mr8313244pbc.160.1442593648815; Fri, 18 Sep 2015 09:27:28 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id la4sm9847027pbc.76.2015.09.18.09.27.27 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 09:27:28 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Cc: adrian.hunter@intel.com, zhang.chunyan@linaro.org, mike.leach@arm.com, tor@ti.com, al.grant@arm.com, pawel.moll@arm.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 19/20] coresight: etm3x: implementing perf's user/kernel mode Date: Fri, 18 Sep 2015 10:26:33 -0600 Message-Id: <1442593594-10665-20-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Configure tracers in accordance with the specification conveyed by the perf cmd line tool. For example if only user space is requested, configure the address range comparator with the kerne's address range and set the 'exclude' bit, which will result in tracing everything except the kernel. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 077b49714259..2f818dbde099 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -320,6 +320,41 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, { u64 config = event->attr.config; + if (event->attr.exclude_kernel || event->attr.exclude_user) { + u32 event_encoding; + u32 flags = (1 << 0 | /* instruction execute*/ + 3 << 3 | /* ARM instruction */ + 0 << 5 | /* No data value comparison */ + 0 << 7 | /* No exact mach */ + 0 << 8 | /* Ignore context ID */ + 0 << 10); /* Security ignored */ + + /* Bit 0 is address range comparator 1 */ + drvdata->enable_ctrl1 = ETMTECR1_ADDR_COMP_1; + + /* Bit 24 controls whether the address range should be + * included or excluded. + */ + if (event->attr.exclude_kernel) + drvdata->enable_ctrl1 |= BIT(24); + + /* No need to worry about single address comparators */ + drvdata->enable_ctrl2 = 0x0; + + drvdata->addr_val[0] = (u32) _stext; + drvdata->addr_val[1] = (u32) _etext; + drvdata->addr_acctype[0] = flags; + drvdata->addr_acctype[1] = flags; + drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE; + drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE; + + event_encoding = 0x00 << 14 | /* Boolean function select A */ + 0x01 << 4 | /* Addr range comparator 0-7 */ + 0x00 << 0; /* Addr range comparator 1 */ + + drvdata->enable_event = event_encoding; + } + /* * At this time only cycle accurate and timestamp options are * available. As such clear everything else that may have been @@ -362,6 +397,7 @@ static void etm_configure_cpu(void *info) etm_writel(drvdata, drvdata->startstop_ctrl, ETMTSSCR); etm_writel(drvdata, drvdata->enable_event, ETMTEEVR); etm_writel(drvdata, drvdata->enable_ctrl1, ETMTECR1); + etm_writel(drvdata, drvdata->enable_ctrl2, ETMTECR2); etm_writel(drvdata, drvdata->fifofull_level, ETMFFLR); for (i = 0; i < drvdata->nr_addr_cmp; i++) { etm_writel(drvdata, drvdata->addr_val[i], ETMACVRn(i));