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[2001:1868:205::9]) by mx.google.com with ESMTPS id rt4si14772752pbb.18.2015.09.18.09.30.16 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Sep 2015 09:30:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyX0-0003ZO-JR; Fri, 18 Sep 2015 16:29:02 +0000 Received: from mail-pa0-f52.google.com ([209.85.220.52]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyVY-0001Rn-JB for linux-arm-kernel@lists.infradead.org; Fri, 18 Sep 2015 16:27:33 +0000 Received: by pacex6 with SMTP id ex6so55403706pac.0 for ; Fri, 18 Sep 2015 09:27:11 -0700 (PDT) X-Received: by 10.68.235.99 with SMTP id ul3mr8266417pbc.138.1442593631818; Fri, 18 Sep 2015 09:27:11 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id la4sm9847027pbc.76.2015.09.18.09.27.10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 09:27:11 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Subject: [RFC PATCH 07/20] coresight: etb10: implementing the setup_aux() API Date: Fri, 18 Sep 2015 10:26:21 -0600 Message-Id: <1442593594-10665-8-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150918_092732_789841_F692045C X-CRM114-Status: GOOD ( 16.63 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.52 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.52 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: al.grant@arm.com, pawel.moll@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Adding an ETB10 specific auxiliary area setup operation to be used by the perf framework when events are initialised. Part of this operation involves modeling the mmap'ed area based on the specific ways a sink buffer gathers information. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 55 +++++++++++++++++++++++++++ include/linux/coresight.h | 3 ++ 2 files changed, 58 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 77d0f9c1118d..ca2fbf65a454 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -27,6 +27,9 @@ #include #include #include +#include + +#include #include "coresight-priv.h" @@ -64,6 +67,32 @@ #define ETB_FRAME_SIZE_WORDS 4 /** + * struct cs_buffer - keep track of a recording session' specifics + * @cur: index of the current buffer + * @nr_pages: max number of pages granted to us + * @nr_bufs: number of clustered pages + * @offset: offset within the current buffer + * @size: how much space we have for this run + * @data_size: how much we collected in this run + * @head: head of the ring buffer + * @lost: other than zero if we had a HW buffer wrap around + * @snapshot: is this run in snapshot mode + * @addr: virtual address this buffer starts at + */ +struct cs_buffers { + unsigned int cur; + unsigned int nr_pages; + unsigned int nr_bufs; + unsigned long offset; + unsigned long size; + local_t data_size; + local_t head; + local_t lost; + bool snapshot; + void *addr[0]; +}; + +/** * struct etb_drvdata - specifics associated to an ETB component * @base: memory mapped base address for this component. * @dev: the device entity associated to this component. @@ -252,9 +281,35 @@ static void etb_disable(struct coresight_device *csdev) dev_info(drvdata->dev, "ETB disabled\n"); } +static void *etb_setup_aux(struct coresight_device *csdev, int cpu, + void **pages, int nr_pages, bool overwrite) +{ + int node, pg; + struct cs_buffers *buf; + + if (cpu == -1) + cpu = smp_processor_id(); + node = cpu_to_node(cpu); + + buf = kzalloc_node(offsetof(struct cs_buffers, addr[nr_pages]), + GFP_KERNEL, node); + if (!buf) + return NULL; + + buf->snapshot = overwrite; + buf->nr_pages = nr_pages; + + /* Record information about buffers */ + for (pg = 0; pg < buf->nr_pages; pg++) + buf->addr[pg] = pages[pg]; + + return buf; +} + static const struct coresight_ops_sink etb_sink_ops = { .enable = etb_enable, .disable = etb_disable, + .setup_aux = etb_setup_aux, }; static const struct coresight_ops etb_cs_ops = { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 9fe2ccf1cc36..71cc23709422 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -185,10 +185,13 @@ struct coresight_device { * Operations available for sinks * @enable: enables the sink. * @disable: disables the sink. + * @setup_aux: initialises perf's ring buffer for trace collection. */ struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev); void (*disable)(struct coresight_device *csdev); + void *(*setup_aux)(struct coresight_device *csdev, int cpu, + void **pages, int nr_pages, bool overwrite); }; /**