diff mbox series

[v2,2/2] clk: qcom: clk-alpha-pll: Update to use determine rate ops for PLL

Message ID 20220202174213.21259-2-tdas@codeaurora.org
State New
Headers show
Series [v2,1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG | expand

Commit Message

Taniya Das Feb. 2, 2022, 5:42 p.m. UTC
On 32 bit devices, where the PLL requires to support the frequency
beyond the range of the `long int` the round rate ops cannot support.
Thus update the clk_ops to use determine rate instead.

Fixes: 134b55b7e19f8 ("clk: qcom: support Huayra type Alpha PLL")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

Comments

Stephen Boyd Feb. 17, 2022, 11:17 p.m. UTC | #1
Quoting Taniya Das (2022-02-02 09:42:13)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 4406cf609aae..4e2e93cd8c8b 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -812,12 +812,25 @@ static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
>         return 0;
>  }
> 
> -static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
> -                                       unsigned long *prate)
> +static int alpha_pll_huayra_determine_rate(struct clk_hw *hw,
> +                                       struct clk_rate_request *req)
>  {
> +       struct clk_hw *parent_hw;
> +       unsigned long rrate, prate;
>         u32 l, a;
> 
> -       return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
> +       parent_hw = clk_hw_get_parent(hw);

The clk_rate_request should already have the parent_hw pointer set in
it. See clk_core_init_rate_req(). So there's no need to
clk_hw_get_parent() again here.

> +       if (!parent_hw)
> +               return -EINVAL;
> +
> +       prate = clk_hw_get_rate(parent_hw);

And low and behold the parent rate is also prepopulated in 'req'. Just
use that.

> +       rrate = alpha_huayra_pll_round_rate(req->rate, prate, &l, &a);
> +
> +       req->best_parent_hw = parent_hw;

Remove.

> +       req->best_parent_rate = prate;

Remove.

> +       req->rate = rrate;

Keep.

	req->rate = alpha_pll_huayra_round_rate(req->rate, prate, &l, &a);

> +
> +       return 0;
>  }
> 
>  static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 4406cf609aae..4e2e93cd8c8b 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -812,12 +812,25 @@  static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
 	return 0;
 }

-static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
-					unsigned long *prate)
+static int alpha_pll_huayra_determine_rate(struct clk_hw *hw,
+					struct clk_rate_request *req)
 {
+	struct clk_hw *parent_hw;
+	unsigned long rrate, prate;
 	u32 l, a;

-	return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
+	parent_hw = clk_hw_get_parent(hw);
+	if (!parent_hw)
+		return -EINVAL;
+
+	prate = clk_hw_get_rate(parent_hw);
+	rrate = alpha_huayra_pll_round_rate(req->rate, prate, &l, &a);
+
+	req->best_parent_hw = parent_hw;
+	req->best_parent_rate = prate;
+	req->rate = rrate;
+
+	return 0;
 }

 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
@@ -946,7 +959,7 @@  const struct clk_ops clk_alpha_pll_huayra_ops = {
 	.disable = clk_alpha_pll_disable,
 	.is_enabled = clk_alpha_pll_is_enabled,
 	.recalc_rate = alpha_pll_huayra_recalc_rate,
-	.round_rate = alpha_pll_huayra_round_rate,
+	.determine_rate = alpha_pll_huayra_determine_rate,
 	.set_rate = alpha_pll_huayra_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);