From patchwork Mon Sep 28 12:37:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 54197 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f69.google.com (mail-la0-f69.google.com [209.85.215.69]) by patches.linaro.org (Postfix) with ESMTPS id DAAFA22DEE for ; Mon, 28 Sep 2015 12:39:19 +0000 (UTC) Received: by laka1 with SMTP id a1sf48789247lak.0 for ; Mon, 28 Sep 2015 05:39:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=2txYHfEz5+vCtbTaXIOjdU0NEqCXwwSJBn/iHg30wb0=; b=jtyO3CTztpdoVFp0h1Q7Yp6UDsRbEgQy7xhE5tne3G/FGoUrcbAtPmsvtquAz3pxVi VVbAwOQeZpE3kUtLFuE7VKK7hKUi33mMm/KfKjhX2B3Vo93JMD8iS9Djj0T6XQLb33Q4 UHa/YlHZunXiYgoskcfeMaJkciDtvnb+XVE00RrGD4dzd196fDvscmS3xyykEuaTi6tg s96diJ3t2M9rkXxiT4CkYsBRgXN1AbMiXlJP+1w6zj1D3U6OUBfB/X+O11midxaC59RY tBtrjQzMgGwI2xCUpmPPmvjH5tIiAiRg1haOyeirfGJiEi4mKUIN1ddOqE4WyXQyTVaa pWCw== X-Gm-Message-State: ALoCoQlXulLOuA/OYPH1OEpdPeUSQNYhPdAIaO7C420NcyuHAIpYYpbNaxApR06DfznA/o1NKG4F X-Received: by 10.112.145.3 with SMTP id sq3mr3256914lbb.7.1443443958850; Mon, 28 Sep 2015 05:39:18 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.18.196 with SMTP id y4ls262245lad.34.gmail; Mon, 28 Sep 2015 05:39:18 -0700 (PDT) X-Received: by 10.152.37.162 with SMTP id z2mr5374329laj.117.1443443958681; Mon, 28 Sep 2015 05:39:18 -0700 (PDT) Received: from mail-la0-f42.google.com (mail-la0-f42.google.com. [209.85.215.42]) by mx.google.com with ESMTPS id g73si8158474lfi.47.2015.09.28.05.39.18 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Sep 2015 05:39:18 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) client-ip=209.85.215.42; Received: by laer8 with SMTP id r8so29250011lae.2 for ; Mon, 28 Sep 2015 05:39:18 -0700 (PDT) X-Received: by 10.25.40.130 with SMTP id o124mr3517896lfo.41.1443443958534; Mon, 28 Sep 2015 05:39:18 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp1534876lbq; Mon, 28 Sep 2015 05:39:17 -0700 (PDT) X-Received: by 10.50.29.101 with SMTP id j5mr14747148igh.70.1443443956881; Mon, 28 Sep 2015 05:39:16 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id qs1si11376091igb.80.2015.09.28.05.39.16; Mon, 28 Sep 2015 05:39:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933635AbbI1Miz (ORCPT + 30 others); Mon, 28 Sep 2015 08:38:55 -0400 Received: from mail-wi0-f180.google.com ([209.85.212.180]:32998 "EHLO mail-wi0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933608AbbI1Miw (ORCPT ); Mon, 28 Sep 2015 08:38:52 -0400 Received: by wiclk2 with SMTP id lk2so102994954wic.0 for ; Mon, 28 Sep 2015 05:38:51 -0700 (PDT) X-Received: by 10.180.186.10 with SMTP id fg10mr18825593wic.30.1443443931164; Mon, 28 Sep 2015 05:38:51 -0700 (PDT) Received: from localhost.localdomain ([31.123.20.10]) by smtp.gmail.com with ESMTPSA id t7sm18129171wib.1.2015.09.28.05.38.49 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Sep 2015 05:38:50 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com Cc: peter.griffin@linaro.org, lee.jones@linaro.org, devicetree@vger.kernel.org, Giuseppe Cavallaro Subject: [PATCH v2 10/11] ARM: DT: STiH407: Add RMII pinctrl support Date: Mon, 28 Sep 2015 13:37:46 +0100 Message-Id: <1443443867-4099-11-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1443443867-4099-1-git-send-email-peter.griffin@linaro.org> References: <1443443867-4099-1-git-send-email-peter.griffin@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.griffin@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds the RMII pinctrl support for the Synopsys MAC on STiH407 SoCs. Signed-off-by: Giuseppe Cavallaro Signed-off-by: Peter Griffin Acked-by: Lee Jones Acked-by: Patrice Chotard --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 9daab1f..881e94a 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -256,6 +256,33 @@ phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; }; }; + + pinctrl_rmii1: rmii1-0 { + st,pins { + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + mdint = <&pio1 3 ALT1 IN BYPASS 0>; + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + + pinctrl_rmii1_phyclk: rmii1_phyclk { + st,pins { + phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; + }; + }; + + pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { + st,pins { + phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; + }; + }; }; pwm1 {