[06/10] net: gmac_rk3288: Add RK3288 GMAC driver

Message ID 1443692893-19905-7-git-send-email-sjoerd.simons@collabora.co.uk
State New
Headers show

Commit Message

Sjoerd Simons Oct. 1, 2015, 9:48 a.m.
Add a new driver for the GMAC ethernet interface present in Rockchip
RK3288 SOCs. This driver subclasses the generic design-ware driver to
add the glue needed specifically for Rockchip.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
---

 drivers/net/Kconfig       |   7 +++
 drivers/net/Makefile      |   1 +
 drivers/net/gmac_rk3288.c | 140 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 148 insertions(+)
 create mode 100644 drivers/net/gmac_rk3288.c

Comments

Bin Meng Oct. 1, 2015, 11:30 a.m. | #1
Hi Sjoerd,

On Thu, Oct 1, 2015 at 5:48 PM, Sjoerd Simons
<sjoerd.simons@collabora.co.uk> wrote:
> Add a new driver for the GMAC ethernet interface present in Rockchip
> RK3288 SOCs. This driver subclasses the generic design-ware driver to
> add the glue needed specifically for Rockchip.
>
> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> ---
>
>  drivers/net/Kconfig       |   7 +++
>  drivers/net/Makefile      |   1 +
>  drivers/net/gmac_rk3288.c | 140 ++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 148 insertions(+)
>  create mode 100644 drivers/net/gmac_rk3288.c
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index bbec6a6..312c660 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -92,4 +92,11 @@ config PCH_GBE
>           This MAC is present in Intel Platform Controller Hub EG20T. It
>           supports 10/100/1000 Mbps operation.
>
> +config GMAC_RK3288
> +       bool "Rockchip RK3288 Synopsys Designware Ethernet MAC"
> +       depends on DM_ETH && ETH_DESIGNWARE
> +       help
> +         This driver provides Rockchip RK3288 network support based on the
> +         Synopsys Designware driver.
> +
>  endif # NETDEVICES
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 150470c..f0a3992 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -32,6 +32,7 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o
>  obj-$(CONFIG_FTMAC110) += ftmac110.o
>  obj-$(CONFIG_FTMAC100) += ftmac100.o
>  obj-$(CONFIG_GRETH) += greth.o
> +obj-$(CONFIG_GMAC_RK3288) += gmac_rk3288.o
>  obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
>  obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
>  obj-$(CONFIG_LAN91C96) += lan91c96.o
> diff --git a/drivers/net/gmac_rk3288.c b/drivers/net/gmac_rk3288.c
> new file mode 100644
> index 0000000..6e92c8e
> --- /dev/null
> +++ b/drivers/net/gmac_rk3288.c
> @@ -0,0 +1,140 @@
> +/*
> + * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +/*
> + * Rockchip GMAC ethernet IP driver for U-Boot
> + */

nits: please use one-line comment format for this.

> +#include <common.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <asm/gpio.h>
> +#include <clk.h>
> +#include <phy.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/grf_rk3288.h>
> +#include "designware.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct gmac_rk3288_platdata {
> +       struct dw_eth_pdata dw_eth_pdata;
> +       int tx_delay;
> +       int rx_delay;
> +};
> +
> +static int gmac_rk3288_ofdata_to_platdata(struct udevice *dev)
> +{
> +       struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
> +
> +       pdata->tx_delay = fdtdec_get_int (gd->fdt_blob, dev->of_offset,

nits: please remove the space after fdtdec_get_int

> +               "tx_delay", 0x30);

nits: and to make this indention match the opening ( above

> +       pdata->rx_delay = fdtdec_get_int (gd->fdt_blob, dev->of_offset,
> +               "rx_delay", 0x10);

nits: ditto

> +
> +       return designware_eth_ofdata_to_platdata(dev);
> +}
> +
> +static int gmac_rk3288_started(struct udevice *dev)
> +{
> +       struct rk3288_grf *grf;
> +       struct dw_eth_dev *priv = dev_get_priv(dev);
> +       int clk;
> +
> +       switch (priv->phydev->speed) {
> +       case 10:
> +               clk = GMAC_CLK_SEL_2_5M;
> +               break;
> +       case 100:
> +               clk = GMAC_CLK_SEL_25M;
> +               break;
> +       case 1000:
> +               clk = GMAC_CLK_SEL_125M;
> +               break;
> +       default:
> +               printf("Unknown phy speed: %d\n", priv->phydev->speed);
> +               return -EINVAL;
> +       }
> +
> +       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +
> +       rk_clrsetreg(&grf->soc_con1,
> +                    GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT,
> +                    clk << GMAC_CLK_SEL_SHIFT);
> +
> +       return 0;
> +}
> +
> +static int gmac_rk3288_probe(struct udevice *dev)
> +{
> +       int ret;
> +       struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
> +       struct dw_eth_dev *priv = dev_get_priv(dev);
> +       enum periph_id periph_id;
> +       struct udevice *pinctrl, *clk;
> +       struct rk3288_grf *grf;
> +
> +       ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> +       if (ret)
> +               return ret;
> +
> +       ret  = pinctrl_get_periph_id(pinctrl, dev);
> +       if (ret < 0)
> +               return ret;
> +
> +       periph_id = ret;
> +       ret = pinctrl_request(pinctrl, periph_id, 0);
> +       if (ret)
> +               return ret;
> +
> +       ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &clk);
> +       if (ret)
> +               return ret;
> +
> +       ret = clk_set_periph_rate(clk, periph_id, 0);
> +       if (ret)
> +               return ret;
> +
> +       /* Set to RGMII mode */
> +       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +       rk_clrsetreg(&grf->soc_con1,
> +                    RMII_MODE_MASK << RMII_MODE_SHIFT |
> +                    GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT,
> +                    GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT);
> +
> +       rk_clrsetreg(&grf->soc_con3,
> +                    RXCLK_DLY_ENA_GMAC_MASK <<  RXCLK_DLY_ENA_GMAC_SHIFT |
> +                    TXCLK_DLY_ENA_GMAC_MASK <<  TXCLK_DLY_ENA_GMAC_SHIFT |
> +                    CLK_RX_DL_CFG_GMAC_MASK <<  CLK_RX_DL_CFG_GMAC_SHIFT |
> +                    CLK_TX_DL_CFG_GMAC_MASK <<  CLK_TX_DL_CFG_GMAC_SHIFT,
> +                    RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT |
> +                    TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT |
> +                    pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT |
> +                    pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT);
> +
> +       priv->started = gmac_rk3288_started;
> +
> +       return designware_eth_probe(dev);
> +}
> +
> +static const struct udevice_id rk3288_gmac_ids[] = {
> +       { .compatible = "rockchip,rk3288-gmac" },
> +       { }
> +};
> +
> +U_BOOT_DRIVER(eth_gmac_rk3288) = {
> +       .name   = "gmac_rk3288",
> +       .id     = UCLASS_ETH,
> +       .of_match = rk3288_gmac_ids,
> +       .ofdata_to_platdata = gmac_rk3288_ofdata_to_platdata,
> +       .probe  = gmac_rk3288_probe,
> +       .ops    = &designware_eth_ops,
> +       .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
> +       .platdata_auto_alloc_size = sizeof(struct gmac_rk3288_platdata),
> +.flags = DM_FLAG_ALLOC_PRIV_DMA,

nits: please indent.

> +};
> --

Regards,
Bin
Simon Glass Oct. 3, 2015, 2:30 p.m. | #2
Hi Sjoerd,

On 1 October 2015 at 10:48, Sjoerd Simons <sjoerd.simons@collabora.co.uk> wrote:
> Add a new driver for the GMAC ethernet interface present in Rockchip
> RK3288 SOCs. This driver subclasses the generic design-ware driver to
> add the glue needed specifically for Rockchip.
>
> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> ---
>
>  drivers/net/Kconfig       |   7 +++
>  drivers/net/Makefile      |   1 +
>  drivers/net/gmac_rk3288.c | 140 ++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 148 insertions(+)
>  create mode 100644 drivers/net/gmac_rk3288.c

Apart from Bin's nits:

Acked-by: Simon Glass <sjg@chromium.org>

>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index bbec6a6..312c660 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -92,4 +92,11 @@ config PCH_GBE
>           This MAC is present in Intel Platform Controller Hub EG20T. It
>           supports 10/100/1000 Mbps operation.
>
> +config GMAC_RK3288
> +       bool "Rockchip RK3288 Synopsys Designware Ethernet MAC"
> +       depends on DM_ETH && ETH_DESIGNWARE
> +       help
> +         This driver provides Rockchip RK3288 network support based on the
> +         Synopsys Designware driver.
> +
>  endif # NETDEVICES
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 150470c..f0a3992 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -32,6 +32,7 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o
>  obj-$(CONFIG_FTMAC110) += ftmac110.o
>  obj-$(CONFIG_FTMAC100) += ftmac100.o
>  obj-$(CONFIG_GRETH) += greth.o
> +obj-$(CONFIG_GMAC_RK3288) += gmac_rk3288.o
>  obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
>  obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
>  obj-$(CONFIG_LAN91C96) += lan91c96.o
> diff --git a/drivers/net/gmac_rk3288.c b/drivers/net/gmac_rk3288.c
> new file mode 100644
> index 0000000..6e92c8e
> --- /dev/null
> +++ b/drivers/net/gmac_rk3288.c
> @@ -0,0 +1,140 @@
> +/*
> + * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +/*
> + * Rockchip GMAC ethernet IP driver for U-Boot
> + */
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <asm/gpio.h>
> +#include <clk.h>
> +#include <phy.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/grf_rk3288.h>
> +#include "designware.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct gmac_rk3288_platdata {
> +       struct dw_eth_pdata dw_eth_pdata;
> +       int tx_delay;
> +       int rx_delay;
> +};
> +
> +static int gmac_rk3288_ofdata_to_platdata(struct udevice *dev)
> +{
> +       struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
> +
> +       pdata->tx_delay = fdtdec_get_int (gd->fdt_blob, dev->of_offset,
> +               "tx_delay", 0x30);
> +       pdata->rx_delay = fdtdec_get_int (gd->fdt_blob, dev->of_offset,
> +               "rx_delay", 0x10);
> +
> +       return designware_eth_ofdata_to_platdata(dev);
> +}
> +
> +static int gmac_rk3288_started(struct udevice *dev)
> +{
> +       struct rk3288_grf *grf;
> +       struct dw_eth_dev *priv = dev_get_priv(dev);
> +       int clk;
> +
> +       switch (priv->phydev->speed) {
> +       case 10:
> +               clk = GMAC_CLK_SEL_2_5M;
> +               break;
> +       case 100:
> +               clk = GMAC_CLK_SEL_25M;
> +               break;
> +       case 1000:
> +               clk = GMAC_CLK_SEL_125M;
> +               break;
> +       default:
> +               printf("Unknown phy speed: %d\n", priv->phydev->speed);
> +               return -EINVAL;
> +       }
> +
> +       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +
> +       rk_clrsetreg(&grf->soc_con1,
> +                    GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT,
> +                    clk << GMAC_CLK_SEL_SHIFT);
> +
> +       return 0;
> +}
> +
> +static int gmac_rk3288_probe(struct udevice *dev)
> +{
> +       int ret;
> +       struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
> +       struct dw_eth_dev *priv = dev_get_priv(dev);
> +       enum periph_id periph_id;
> +       struct udevice *pinctrl, *clk;
> +       struct rk3288_grf *grf;
> +
> +       ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> +       if (ret)
> +               return ret;
> +
> +       ret  = pinctrl_get_periph_id(pinctrl, dev);
> +       if (ret < 0)
> +               return ret;
> +
> +       periph_id = ret;
> +       ret = pinctrl_request(pinctrl, periph_id, 0);
> +       if (ret)
> +               return ret;
> +
> +       ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &clk);
> +       if (ret)
> +               return ret;
> +
> +       ret = clk_set_periph_rate(clk, periph_id, 0);
> +       if (ret)
> +               return ret;
> +
> +       /* Set to RGMII mode */
> +       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +       rk_clrsetreg(&grf->soc_con1,
> +                    RMII_MODE_MASK << RMII_MODE_SHIFT |
> +                    GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT,
> +                    GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT);
> +
> +       rk_clrsetreg(&grf->soc_con3,
> +                    RXCLK_DLY_ENA_GMAC_MASK <<  RXCLK_DLY_ENA_GMAC_SHIFT |
> +                    TXCLK_DLY_ENA_GMAC_MASK <<  TXCLK_DLY_ENA_GMAC_SHIFT |
> +                    CLK_RX_DL_CFG_GMAC_MASK <<  CLK_RX_DL_CFG_GMAC_SHIFT |
> +                    CLK_TX_DL_CFG_GMAC_MASK <<  CLK_TX_DL_CFG_GMAC_SHIFT,
> +                    RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT |
> +                    TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT |
> +                    pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT |
> +                    pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT);
> +
> +       priv->started = gmac_rk3288_started;
> +
> +       return designware_eth_probe(dev);
> +}
> +
> +static const struct udevice_id rk3288_gmac_ids[] = {
> +       { .compatible = "rockchip,rk3288-gmac" },
> +       { }
> +};
> +
> +U_BOOT_DRIVER(eth_gmac_rk3288) = {
> +       .name   = "gmac_rk3288",
> +       .id     = UCLASS_ETH,
> +       .of_match = rk3288_gmac_ids,
> +       .ofdata_to_platdata = gmac_rk3288_ofdata_to_platdata,
> +       .probe  = gmac_rk3288_probe,
> +       .ops    = &designware_eth_ops,
> +       .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
> +       .platdata_auto_alloc_size = sizeof(struct gmac_rk3288_platdata),
> +.flags = DM_FLAG_ALLOC_PRIV_DMA,
> +};
> --
> 2.5.3
>

Regards,
Simon

Patch

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index bbec6a6..312c660 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -92,4 +92,11 @@  config PCH_GBE
 	  This MAC is present in Intel Platform Controller Hub EG20T. It
 	  supports 10/100/1000 Mbps operation.
 
+config GMAC_RK3288
+	bool "Rockchip RK3288 Synopsys Designware Ethernet MAC"
+	depends on DM_ETH && ETH_DESIGNWARE
+	help
+	  This driver provides Rockchip RK3288 network support based on the
+	  Synopsys Designware driver.
+
 endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 150470c..f0a3992 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -32,6 +32,7 @@  obj-$(CONFIG_FTGMAC100) += ftgmac100.o
 obj-$(CONFIG_FTMAC110) += ftmac110.o
 obj-$(CONFIG_FTMAC100) += ftmac100.o
 obj-$(CONFIG_GRETH) += greth.o
+obj-$(CONFIG_GMAC_RK3288) += gmac_rk3288.o
 obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
 obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
 obj-$(CONFIG_LAN91C96) += lan91c96.o
diff --git a/drivers/net/gmac_rk3288.c b/drivers/net/gmac_rk3288.c
new file mode 100644
index 0000000..6e92c8e
--- /dev/null
+++ b/drivers/net/gmac_rk3288.c
@@ -0,0 +1,140 @@ 
+/*
+ * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Rockchip GMAC ethernet IP driver for U-Boot
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <asm/gpio.h>
+#include <clk.h>
+#include <phy.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3288.h>
+#include "designware.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct gmac_rk3288_platdata {
+	struct dw_eth_pdata dw_eth_pdata;
+	int tx_delay;
+	int rx_delay;
+};
+
+static int gmac_rk3288_ofdata_to_platdata(struct udevice *dev)
+{
+	struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
+
+	pdata->tx_delay = fdtdec_get_int (gd->fdt_blob, dev->of_offset,
+		"tx_delay", 0x30);
+	pdata->rx_delay = fdtdec_get_int (gd->fdt_blob, dev->of_offset,
+		"rx_delay", 0x10);
+
+	return designware_eth_ofdata_to_platdata(dev);
+}
+
+static int gmac_rk3288_started(struct udevice *dev)
+{
+	struct rk3288_grf *grf;
+	struct dw_eth_dev *priv = dev_get_priv(dev);
+	int clk;
+
+	switch (priv->phydev->speed) {
+	case 10:
+		clk = GMAC_CLK_SEL_2_5M;
+		break;
+	case 100:
+		clk = GMAC_CLK_SEL_25M;
+		break;
+	case 1000:
+		clk = GMAC_CLK_SEL_125M;
+		break;
+	default:
+		printf("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	rk_clrsetreg(&grf->soc_con1,
+		     GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT,
+		     clk << GMAC_CLK_SEL_SHIFT);
+
+	return 0;
+}
+
+static int gmac_rk3288_probe(struct udevice *dev)
+{
+	int ret;
+	struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
+	struct dw_eth_dev *priv = dev_get_priv(dev);
+	enum periph_id periph_id;
+	struct udevice *pinctrl, *clk;
+	struct rk3288_grf *grf;
+
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret)
+		return ret;
+
+	ret  = pinctrl_get_periph_id(pinctrl, dev);
+	if (ret < 0)
+		return ret;
+
+	periph_id = ret;
+	ret = pinctrl_request(pinctrl, periph_id, 0);
+	if (ret)
+		return ret;
+
+	ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &clk);
+	if (ret)
+		return ret;
+
+	ret = clk_set_periph_rate(clk, periph_id, 0);
+	if (ret)
+		return ret;
+
+	/* Set to RGMII mode */
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con1,
+		     RMII_MODE_MASK << RMII_MODE_SHIFT |
+		     GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT,
+		     GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT);
+
+	rk_clrsetreg(&grf->soc_con3,
+		     RXCLK_DLY_ENA_GMAC_MASK <<  RXCLK_DLY_ENA_GMAC_SHIFT |
+		     TXCLK_DLY_ENA_GMAC_MASK <<  TXCLK_DLY_ENA_GMAC_SHIFT |
+		     CLK_RX_DL_CFG_GMAC_MASK <<  CLK_RX_DL_CFG_GMAC_SHIFT |
+		     CLK_TX_DL_CFG_GMAC_MASK <<  CLK_TX_DL_CFG_GMAC_SHIFT,
+		     RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT |
+		     TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT |
+		     pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT |
+		     pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT);
+
+	priv->started = gmac_rk3288_started;
+
+	return designware_eth_probe(dev);
+}
+
+static const struct udevice_id rk3288_gmac_ids[] = {
+	{ .compatible = "rockchip,rk3288-gmac" },
+	{ }
+};
+
+U_BOOT_DRIVER(eth_gmac_rk3288) = {
+	.name	= "gmac_rk3288",
+	.id	= UCLASS_ETH,
+	.of_match = rk3288_gmac_ids,
+	.ofdata_to_platdata = gmac_rk3288_ofdata_to_platdata,
+	.probe	= gmac_rk3288_probe,
+	.ops	= &designware_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
+	.platdata_auto_alloc_size = sizeof(struct gmac_rk3288_platdata),
+.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};