Message ID | 20220227182125.21809-7-richard.henderson@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | target/nios2: Rewrite interrupt handling | expand |
On 27/2/22 19:21, Richard Henderson wrote: > It was never correct to be able to write to ipending. > Until the rest of the irq code is tidied, the read of ipending > will generate an "unnecessary" mask. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/nios2/translate.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On Sun, 27 Feb 2022 at 18:25, Richard Henderson <richard.henderson@linaro.org> wrote: > > It was never correct to be able to write to ipending. > Until the rest of the irq code is tidied, the read of ipending > will generate an "unnecessary" mask. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/nios2/translate.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/nios2/translate.c b/target/nios2/translate.c > index 52965ba17e..b17ce25a36 100644 > --- a/target/nios2/translate.c > +++ b/target/nios2/translate.c > @@ -452,6 +452,15 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) > } > > switch (instr.imm5 + CR_BASE) { > + case CR_IPENDING: > + /* > + * The value of the ipending register is synthetic. > + * In hw, this is the AND of a set of hardware irq lines > + * with the ienable register. In qemu, we re-use the space > + * of CR_IPENDING to store the set of irq lines. maybe add "and so we must perform the AND here, and anywhere else we need the guest value of CR_IPENDING" ? > + */ > + tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABLE]); > + break; Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 52965ba17e..b17ce25a36 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -452,6 +452,15 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) } switch (instr.imm5 + CR_BASE) { + case CR_IPENDING: + /* + * The value of the ipending register is synthetic. + * In hw, this is the AND of a set of hardware irq lines + * with the ienable register. In qemu, we re-use the space + * of CR_IPENDING to store the set of irq lines. + */ + tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABLE]); + break; default: tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); break; @@ -477,6 +486,9 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) case CR_TLBMISC: gen_helper_mmu_write_tlbmisc(cpu_env, v); break; + case CR_IPENDING: + /* ipending is read only, writes ignored. */ + break; default: tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); break;
It was never correct to be able to write to ipending. Until the rest of the irq code is tidied, the read of ipending will generate an "unnecessary" mask. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/nios2/translate.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)