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[2001:1868:205::9]) by mx.google.com with ESMTPS id 16si11691712ion.57.2015.10.15.06.49.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Oct 2015 06:49:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZmitJ-0002IN-4a; Thu, 15 Oct 2015 13:48:21 +0000 Received: from mail-lb0-f174.google.com ([209.85.217.174]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zmisl-0001q5-IQ for linux-arm-kernel@lists.infradead.org; Thu, 15 Oct 2015 13:47:48 +0000 Received: by lbbwb3 with SMTP id wb3so7201669lbb.1 for ; Thu, 15 Oct 2015 06:47:25 -0700 (PDT) X-Received: by 10.112.130.39 with SMTP id ob7mr4693439lbb.66.1444916845516; Thu, 15 Oct 2015 06:47:25 -0700 (PDT) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id ug9sm2056977lbb.22.2015.10.15.06.47.23 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Oct 2015 06:47:24 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Russell King Subject: [PATCH 05/13] irqchip/gic: assign irqchip dynamically Date: Thu, 15 Oct 2015 15:46:45 +0200 Message-Id: <1444916813-31024-6-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1444916813-31024-1-git-send-email-linus.walleij@linaro.org> References: <1444916813-31024-1-git-send-email-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151015_064747_861241_DC87923F X-CRM114-Status: GOOD ( 20.10 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.217.174 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.217.174 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: Mark Rutland , Jason Cooper , Pawel Moll , Marc Zyngier , Linus Walleij , Will Deacon , Thomas Gleixner MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Instead of having the irqchip being a static struct, make it part of the per-instance data so we can assign it a dynamic name. This has the usable side effect of displaying the GIC with an instance number as GIC0, GIC1 ... GICn in /proc/interrupts, which is helpful when debugging cascaded GICs, such as on the ARM PB11MPCore. Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Signed-off-by: Linus Walleij --- Fellas please say what you think about this: Yes / No / Linus is an idiot This can be applied directly to the irqchip tree if you like it, AFAIK it has no dependencies. --- drivers/irqchip/irq-gic.c | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index bd021e1e4847..478279cf9517 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -58,6 +58,7 @@ union gic_base { }; struct gic_chip_data { + struct irq_chip chip; union gic_base dist_base; union gic_base cpu_base; #ifdef CONFIG_CPU_PM @@ -369,22 +370,6 @@ static void gic_handle_cascade_irq(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static struct irq_chip gic_chip = { - .name = "GIC", - .irq_mask = gic_mask_irq, - .irq_unmask = gic_unmask_irq, - .irq_eoi = gic_eoi_irq, - .irq_set_type = gic_set_type, -#ifdef CONFIG_SMP - .irq_set_affinity = gic_set_affinity, -#endif - .irq_get_irqchip_state = gic_irq_get_irqchip_state, - .irq_set_irqchip_state = gic_irq_set_irqchip_state, - .flags = IRQCHIP_SET_TYPE_MASKED | - IRQCHIP_SKIP_SET_WAKE | - IRQCHIP_MASK_ON_SUSPEND, -}; - static struct irq_chip gic_eoimode1_chip = { .name = "GICv2", .irq_mask = gic_eoimode1_mask_irq, @@ -880,7 +865,8 @@ void __init gic_init_physaddr(struct device_node *node) static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { - struct irq_chip *chip = &gic_chip; + struct gic_chip_data *gic = d->host_data; + struct irq_chip *chip = &gic->chip; if (static_key_true(&supports_deactivate)) { if (d->host_data == (void *)&gic_data[0]) @@ -989,6 +975,22 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, BUG_ON(gic_nr >= MAX_GIC_NR); gic = &gic_data[gic_nr]; + + /* Initialize irq_chip */ + gic->chip.name = kasprintf(GFP_KERNEL, "GIC%d", gic_nr); + gic->chip.irq_mask = gic_mask_irq; + gic->chip.irq_unmask = gic_unmask_irq; + gic->chip.irq_eoi = gic_eoi_irq; + gic->chip.irq_set_type = gic_set_type; +#ifdef CONFIG_SMP + gic->chip.irq_set_affinity = gic_set_affinity; +#endif + gic->chip.irq_get_irqchip_state = gic_irq_get_irqchip_state; + gic->chip.irq_set_irqchip_state = gic_irq_set_irqchip_state; + gic->chip.flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND; + #ifdef CONFIG_GIC_NON_BANKED if (percpu_offset) { /* Frankein-GIC without banked registers... */ unsigned int cpu;