@@ -70,6 +70,13 @@ static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
}
}
+static inline bool spi_nor_is_octal_dtr_swab16(const struct spi_nor *nor,
+ enum spi_nor_protocol proto)
+{
+ return (proto == SNOR_PROTO_8_8_8_DTR) &&
+ (nor->flags & SNOR_F_DTR_SWAB16);
+}
+
/**
* spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
* @nor: pointer to a 'struct spi_nor'
@@ -105,6 +112,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor,
op->addr.dtr = true;
op->dummy.dtr = true;
op->data.dtr = true;
+ op->data.dtr_swab16 = spi_nor_is_octal_dtr_swab16(nor, proto);
/* 2 bytes per clock cycle in DTR mode. */
op->dummy.nbytes *= 2;
@@ -135,6 +135,7 @@ enum spi_nor_option_flags {
SNOR_F_IO_MODE_EN_VOLATILE = BIT(11),
SNOR_F_SOFT_RESET = BIT(12),
SNOR_F_SWP_IS_VOLATILE = BIT(13),
+ SNOR_F_DTR_SWAB16 = BIT(14),
};
struct spi_nor_read_command {
Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. The byte order of 16-bit words is swapped when read or written in 8D-8D-8D mode compared to STR modes. Allow operations to specify the byte order in DTR mode, so that controllers can swap the bytes back at run-time to address the flash's endianness requirements, if they are capable. If the controllers are not capable of swapping the bytes, the protocol is downgraded via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the bytes is always done regardless if it's a data or register access, so that we comply with the JESD216 requirements: "Byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1". Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- drivers/mtd/spi-nor/core.c | 8 ++++++++ drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 9 insertions(+)