From patchwork Tue Dec 6 04:38:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob X-Patchwork-Id: 5509 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8BEB423E10 for ; Tue, 6 Dec 2011 04:38:31 +0000 (UTC) Received: from mail-lpp01m010-f52.google.com (mail-lpp01m010-f52.google.com [209.85.215.52]) by fiordland.canonical.com (Postfix) with ESMTP id 71560A18643 for ; Tue, 6 Dec 2011 04:38:31 +0000 (UTC) Received: by mail-lpp01m010-f52.google.com with SMTP id m6so727409lag.11 for ; Mon, 05 Dec 2011 20:38:31 -0800 (PST) Received: by 10.152.122.34 with SMTP id lp2mr7945643lab.20.1323146311318; Mon, 05 Dec 2011 20:38:31 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs296311lal; Mon, 5 Dec 2011 20:38:31 -0800 (PST) Received: by 10.224.34.202 with SMTP id m10mr10451692qad.62.1323146309323; Mon, 05 Dec 2011 20:38:29 -0800 (PST) Received: from mail-qw0-f50.google.com (mail-qw0-f50.google.com [209.85.216.50]) by mx.google.com with ESMTPS id w6si6554759qcv.55.2011.12.05.20.38.28 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Dec 2011 20:38:29 -0800 (PST) Received-SPF: neutral (google.com: 209.85.216.50 is neither permitted nor denied by best guess record for domain of rob.lee@linaro.org) client-ip=209.85.216.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.216.50 is neither permitted nor denied by best guess record for domain of rob.lee@linaro.org) smtp.mail=rob.lee@linaro.org Received: by mail-qw0-f50.google.com with SMTP id a17so472697qae.16 for ; Mon, 05 Dec 2011 20:38:28 -0800 (PST) Received: by 10.224.32.16 with SMTP id a16mr10461959qad.85.1323146307938; Mon, 05 Dec 2011 20:38:27 -0800 (PST) Received: from b18647-20 ([23.19.172.17]) by mx.google.com with ESMTPS id fm5sm29806936qab.20.2011.12.05.20.38.26 (version=SSLv3 cipher=OTHER); Mon, 05 Dec 2011 20:38:27 -0800 (PST) From: Robert Lee To: linux@arm.linux.org.uk, s.hauer@pengutronix.de Cc: shawn.guo@freescale.com, nicolas.ferre@atmel.com, linux@maxim.org.za, kgene.kim@samsung.com, amit.kachhap@linaro.org, magnus.damm@gmail.com, khilman@ti.com, nsekhar@ti.com, daniel.lezcano@linaro.org, mturquette@linaro.org, vincent.guittot@linaro.org, arnd.bergmann@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org Subject: [RFC PATCH 7/8] ARM: imx: Add mx5 clock changes necessary for low power Date: Mon, 5 Dec 2011 22:38:10 -0600 Message-Id: <1323146291-10676-8-git-send-email-rob.lee@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1323146291-10676-1-git-send-email-rob.lee@linaro.org> References: <1323146291-10676-1-git-send-email-rob.lee@linaro.org> Add mx5 clock changes necessary to enter low power operating modes. Signed-off-by: Robert Lee --- arch/arm/mach-mx5/clock-mx51-mx53.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 4cb2769..12c8a2b 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1533,6 +1533,7 @@ static struct clk_lookup mx53_lookups[] = { _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk) _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk) _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk) + _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) }; static void clk_tree_init(void) @@ -1572,6 +1573,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&cpu_clk); clk_enable(&main_bus_clk); + clk_enable(&gpc_dvfs_clk); clk_enable(&iim_clk); imx_print_silicon_rev("i.MX51", mx51_revision()); @@ -1615,6 +1617,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, clk_set_parent(&uart_root_clk, &pll3_sw_clk); clk_enable(&cpu_clk); clk_enable(&main_bus_clk); + clk_enable(&gpc_dvfs_clk); clk_enable(&iim_clk); imx_print_silicon_rev("i.MX53", mx53_revision());