From patchwork Wed Dec 7 20:29:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 5533 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4210023E0E for ; Wed, 7 Dec 2011 20:29:55 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 3264FA18D7E for ; Wed, 7 Dec 2011 20:29:55 +0000 (UTC) Received: by bke17 with SMTP id 17so1204562bke.11 for ; Wed, 07 Dec 2011 12:29:55 -0800 (PST) Received: by 10.204.152.87 with SMTP id f23mr150941bkw.18.1323289794273; Wed, 07 Dec 2011 12:29:54 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs79555bkc; Wed, 7 Dec 2011 12:29:53 -0800 (PST) Received: by 10.236.131.103 with SMTP id l67mr116087yhi.18.1323289791725; Wed, 07 Dec 2011 12:29:51 -0800 (PST) Received: from relay1.mentorg.com (relay1.mentorg.com. [192.94.38.131]) by mx.google.com with ESMTPS id x8si1397348ani.199.2011.12.07.12.29.51 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Dec 2011 12:29:51 -0800 (PST) Received-SPF: neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) client-ip=192.94.38.131; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) smtp.mail=Andrew_Stubbs@mentor.com Received: from nat-ies.mentorg.com ([192.94.31.2] helo=EU1-MAIL.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1RYO7g-0000dn-M7 from Andrew_Stubbs@mentor.com ; Wed, 07 Dec 2011 12:29:48 -0800 Received: from [172.30.6.20] ([172.30.6.20]) by EU1-MAIL.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 7 Dec 2011 20:29:46 +0000 Message-ID: <4EDFCCB1.9030006@codesourcery.com> Date: Wed, 07 Dec 2011 20:29:37 +0000 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111124 Thunderbird/8.0 MIME-Version: 1.0 To: Richard Earnshaw CC: "gcc-patches@gcc.gnu.org" , "patches@linaro.org" Subject: Re: [PATCH][ARM] one_cmpldi2 in NEON References: <4EDE5810.1070204@codesourcery.com> <4EDF9387.6050503@arm.com> In-Reply-To: <4EDF9387.6050503@arm.com> X-OriginalArrivalTime: 07 Dec 2011 20:29:46.0948 (UTC) FILETIME=[F61A8040:01CCB51E] On 07/12/11 16:25, Richard Earnshaw wrote: >> 2011-12-06 Andrew Stubbs >> >> gcc/ >> * config/arm/arm.md (one_cmpldi2): Rename to ... >> (one_cmpldi2_core): ... this, and modify it to prevent it being >> used for NEON. >> (one_cmpldi2): New define_expand. >> * config/arm/neon.md (one_cmpldi2_neon): New define_insn. > > >> +(define_insn_and_split "*one_cmpldi2_core" >> + [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r") >> + (not:DI (match_operand:DI 1 "arm_general_register_operand" "0,r")))] > > Thinking about it, for an operation with one input and one output, there's no need for the > earlyclobber marker when the input is tied to the output (there's no other operand that can be > clobbered). > > Otherwise OK. Thanks I'll test and commit the attached updated patch once stage 1 opens again. Andrew 2011-12-07 Andrew Stubbs gcc/ * config/arm/arm.md (one_cmpldi2): Rename to ... (one_cmpldi2_core): ... this, and modify it to prevent it being used for NEON. (one_cmpldi2): New define_expand. * config/arm/neon.md (one_cmpldi2_neon): New define_insn. --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4199,10 +4199,16 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)" "") -(define_insn_and_split "one_cmpldi2" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") - (not:DI (match_operand:DI 1 "s_register_operand" "0,r")))] +(define_expand "one_cmpldi2" + [(set (match_operand:DI 0 "s_register_operand" "") + (not:DI (match_operand:DI 1 "s_register_operand" "")))] "TARGET_32BIT" + "") + +(define_insn_and_split "*one_cmpldi2_core" + [(set (match_operand:DI 0 "arm_general_register_operand" "=r,&r") + (not:DI (match_operand:DI 1 "arm_general_register_operand" "0,r")))] + "TARGET_32BIT && !TARGET_NEON" "#" "TARGET_32BIT && reload_completed" [(set (match_dup 0) (not:SI (match_dup 1))) --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -896,6 +896,20 @@ [(set_attr "neon_type" "neon_int_1")] ) +(define_insn "*one_cmpldi2_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w,?r,?&r,?w") + (not:DI (match_operand:DI 1 "s_register_operand" " w, 0, r, w")))] + "TARGET_NEON" + "@ + vmvn\t%P0, %P1 + # + # + vmvn\t%P0, %P1" + [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1") + (set_attr "length" "*,8,8,*") + (set_attr "arch" "nota8,*,*,onlya8")] +) + (define_insn "abs2" [(set (match_operand:VDQW 0 "s_register_operand" "=w") (abs:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]