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[v4,1/2] dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC

Message ID 20220326060810.1797516-2-bhupesh.sharma@linaro.org
State Accepted
Commit a6e25b39adc3f68b9bc46f8e100345ee9bf62f8c
Headers show
Series [v4,1/2] dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC | expand

Commit Message

Bhupesh Sharma March 26, 2022, 6:08 a.m. UTC 
Document the PCIe DT bindings for SM8150 SoC. The PCIe IP is similar to
the one used on SM8250.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 Documentation/devicetree/bindings/pci/qcom,pcie.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
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Patch

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 0adb56d5645e..fd8b6d1912e7 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -14,6 +14,7 @@ 
 			- "qcom,pcie-qcs404" for qcs404
 			- "qcom,pcie-sc8180x" for sc8180x
 			- "qcom,pcie-sdm845" for sdm845
+			- "qcom,pcie-sm8150" for sm8150
 			- "qcom,pcie-sm8250" for sm8250
 			- "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450
 			- "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450
@@ -159,7 +160,7 @@ 
 			- "pipe"	PIPE clock
 
 - clock-names:
-	Usage: required for sc8180x and sm8250
+	Usage: required for sc8180x, sm8150 and sm8250
 	Value type: <stringlist>
 	Definition: Should contain the following entries
 			- "aux"		Auxiliary clock
@@ -266,7 +267,7 @@ 
 			- "ahb"			AHB reset
 
 - reset-names:
-	Usage: required for sc8180x, sdm845, sm8250 and sm8450
+	Usage: required for sc8180x, sdm845, sm8150, sm8250 and sm8450
 	Value type: <stringlist>
 	Definition: Should contain the following entries
 			- "pci"			PCIe core reset