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[2001:1868:205::9]) by mx.google.com with ESMTPS id k3si2355774ige.22.2015.10.23.02.07.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Oct 2015 02:07:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZpYHl-0007LZ-7G; Fri, 23 Oct 2015 09:05:17 +0000 Received: from mail-lf0-f47.google.com ([209.85.215.47]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZpYHh-0006BR-Vf for linux-arm-kernel@lists.infradead.org; Fri, 23 Oct 2015 09:05:15 +0000 Received: by lffv3 with SMTP id v3so76135289lff.0 for ; Fri, 23 Oct 2015 02:04:51 -0700 (PDT) X-Received: by 10.25.28.131 with SMTP id c125mr5607122lfc.99.1445591091206; Fri, 23 Oct 2015 02:04:51 -0700 (PDT) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id o197sm2879941lfb.7.2015.10.23.02.04.49 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Oct 2015 02:04:50 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Russell King , Marc Zyngier Subject: [PATCH 05/13 v2] irqchip/gic: assign irqchip dynamically Date: Fri, 23 Oct 2015 11:04:43 +0200 Message-Id: <1445591083-22494-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151023_020514_224052_7A6A5D02 X-CRM114-Status: GOOD ( 19.80 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.47 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.215.47 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: Mark Rutland , Jason Cooper , Pawel Moll , Linus Walleij , Will Deacon , Thomas Gleixner MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Instead of having the irqchip being a static struct, make it part of the per-instance data so we can assign it a dynamic name. This has the usable side effect of displaying the GIC with an instance number as GIC0, GIC1 ... GICn in /proc/interrupts, which is helpful when debugging cascaded GICs, such as on the ARM PB11MPCore. Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Keep the static structs around, just delete the .name field assign them to the chips at registration time, updating the name field with the instance number. - Also enumerate the EOIMODE1 sub-chips. Marc: can't test the EOIMODE1 thing, it's far above me, but it "should work". Is it correct that there is one unique and coupled EOIMODE1 instance per GIC instance like this? --- drivers/irqchip/irq-gic.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index bd021e1e4847..8c93ff80ec52 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -58,6 +58,8 @@ union gic_base { }; struct gic_chip_data { + struct irq_chip chip; + struct irq_chip eoimode1_chip; union gic_base dist_base; union gic_base cpu_base; #ifdef CONFIG_CPU_PM @@ -370,7 +372,6 @@ static void gic_handle_cascade_irq(struct irq_desc *desc) } static struct irq_chip gic_chip = { - .name = "GIC", .irq_mask = gic_mask_irq, .irq_unmask = gic_unmask_irq, .irq_eoi = gic_eoi_irq, @@ -386,7 +387,6 @@ static struct irq_chip gic_chip = { }; static struct irq_chip gic_eoimode1_chip = { - .name = "GICv2", .irq_mask = gic_eoimode1_mask_irq, .irq_unmask = gic_unmask_irq, .irq_eoi = gic_eoimode1_eoi_irq, @@ -880,11 +880,12 @@ void __init gic_init_physaddr(struct device_node *node) static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { - struct irq_chip *chip = &gic_chip; + struct gic_chip_data *gic = d->host_data; + struct irq_chip *chip = &gic->chip; if (static_key_true(&supports_deactivate)) { if (d->host_data == (void *)&gic_data[0]) - chip = &gic_eoimode1_chip; + chip = &gic->eoimode1_chip; } if (hw < 32) { @@ -989,6 +990,13 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, BUG_ON(gic_nr >= MAX_GIC_NR); gic = &gic_data[gic_nr]; + + /* Initialize irq_chip */ + gic->chip = gic_chip; + gic->eoimode1_chip = gic_eoimode1_chip; + gic->chip.name = kasprintf(GFP_KERNEL, "GIC%d", gic_nr); + gic->eoimode1_chip.name = kasprintf(GFP_KERNEL, "GICv2%d", gic_nr); + #ifdef CONFIG_GIC_NON_BANKED if (percpu_offset) { /* Frankein-GIC without banked registers... */ unsigned int cpu;