| Message ID | 1648723177-28218-1-git-send-email-loic.poulain@linaro.org |
|---|---|
| State | Accepted |
| Commit | 85d0580e684c74dcb0a90aa0c010006cda40af44 |
| Headers | show |
| Series | imx8ulp: clock: Fix lcd clock algo | expand |
On 2022/3/31 18:39, Loic Poulain wrote: > The div loop uses reassign and reuse parent_rate, which causes > the parent rate reference to be wrong after the first loop, the > resulting clock becomes incorrect for div != 1. > > Fixes: 829e06bf4175 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock") > Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> > --- > arch/arm/mach-imx/imx8ulp/clock.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c > index 91580b2..dbe0f78 100644 > --- a/arch/arm/mach-imx/imx8ulp/clock.c > +++ b/arch/arm/mach-imx/imx8ulp/clock.c > @@ -381,10 +381,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) > debug("PLL4 rate %ukhz\n", pll4_rate); > > for (pfd = 12; pfd <= 35; pfd++) { > - parent_rate = pll4_rate; > - parent_rate = parent_rate * 18 / pfd; > - > for (div = 1; div <= 64; div++) { > + parent_rate = pll4_rate; > + parent_rate = parent_rate * 18 / pfd; > parent_rate = parent_rate / div; > > for (pcd = 0; pcd < 8; pcd++) { >
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 91580b2..dbe0f78 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -381,10 +381,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) debug("PLL4 rate %ukhz\n", pll4_rate); for (pfd = 12; pfd <= 35; pfd++) { - parent_rate = pll4_rate; - parent_rate = parent_rate * 18 / pfd; - for (div = 1; div <= 64; div++) { + parent_rate = pll4_rate; + parent_rate = parent_rate * 18 / pfd; parent_rate = parent_rate / div; for (pcd = 0; pcd < 8; pcd++) {
The div loop uses reassign and reuse parent_rate, which causes the parent rate reference to be wrong after the first loop, the resulting clock becomes incorrect for div != 1. Fixes: 829e06bf4175 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock") Signed-off-by: Loic Poulain <loic.poulain@linaro.org> --- arch/arm/mach-imx/imx8ulp/clock.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)