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[209.132.180.131]) by mx.google.com with ESMTPS id kh9si3157486pab.241.2015.11.11.08.08.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Nov 2015 08:08:07 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-return-89663-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-return-89663-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=binutils-return-89663-patch=linaro.org@sourceware.org; dkim=pass header.i=@sourceware.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id :mime-version:content-type; q=dns; s=default; b=ojxWnqrQB8a12Rrg yS+RF1d5I70A2k8LISkHra1KRNKJRvE55xVF3a6y0qloSUiVwgfBwA41O+oUf53X Tfjj5Ec5GHMF56878xWsxlO+glzyg3GOh0MEzu9I67TUJCJcdyXBI8K8sY8Wf2bv nfMZ3n/psY4HJ+2O9RjvXvX0LWw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id :mime-version:content-type; s=default; bh=GZHgQhYnBqqWsEtko5bk3M +hQNU=; b=QGJ6g50kzJ/4nwgxw0Mat7sJDMf9kEwgPtsKbSkwAqKEYlnXYhidAa oHelyzxopzlSUdzamPGRK7QspvWmXkEinI2Ep4ZSANWQUU88NlGSwUaWPEKEbgwe gFqQiIhXi10wr4uOPnz1SRsOzO/J3VbYwuFaw5gam+UHbrSC1c/rM= Received: (qmail 39244 invoked by alias); 11 Nov 2015 16:07:53 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Delivered-To: mailing list binutils@sourceware.org Received: (qmail 39233 invoked by uid 89); 11 Nov 2015 16:07:52 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 11 Nov 2015 16:07:50 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-20-8-Yr3D8aRCC-IFkUDQbEIg-1; Wed, 11 Nov 2015 16:07:45 +0000 Received: from e107456-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 11 Nov 2015 16:07:44 +0000 From: James Greenhalgh To: binutils@sourceware.org Cc: richard.earnshaw@arm.com, marcus.shawcroft@arm.com Subject: [Patch Gas AArch64] Add support for Cortex-A35 Date: Wed, 11 Nov 2015 16:07:27 +0000 Message-Id: <1447258047-10763-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 8-Yr3D8aRCC-IFkUDQbEIg-1 X-IsSubscribed: yes Hi, This patch adds support to the AArch64 back-end for the Cortex-A35 processor, as recently announced by ARM. The ARM Cortex-A35 provides full support for the ARMv8-A architecture, including the CRC extension, with optional Advanced-SIMD and Floating-Point support. We therefore set feature flags for this CPU to AARCH64_ARCH_V8 and AARCH64_FEATURE_CRC, in the same fashion as Cortex-A53 and Cortex-A57. Tested in a cross environment for AArch64 with no issues. OK? If so, please apply it on my behalf as I don't have write permissions over here. Thanks, James --- 2015-11-11 James Greenhalgh * config/tc-aarch64.c (aarch64_cpus): Add cortex-a35. * doc/c-aarch64.texi (-mcpu=): Likewise. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index b45aac8..e854b96 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -7676,6 +7676,8 @@ struct aarch64_cpu_option_table recognized by GCC. */ static const struct aarch64_cpu_option_table aarch64_cpus[] = { {"all", AARCH64_ANY, NULL}, + {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8, + AARCH64_FEATURE_CRC), "Cortex-A35"}, {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8, AARCH64_FEATURE_CRC), "Cortex-A53"}, {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8, diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index e3ca09d..e7e6ba4 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -55,6 +55,7 @@ file in ELF32 and ELF64 format respectively. The default is @code{lp64}. This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: +@code{cortex-a35}, @code{cortex-a53}, @code{cortex-a57}, @code{cortex-a72},