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[ARM/Aarch64] add initial Qualcomm support

Message ID CABXYE2UE0G9sT_wc+nuzmjpqUCf+2wZZEhh1VcNjO2ON8F-06w@mail.gmail.com
State New
Headers show

Commit Message

Jim Wilson Nov. 11, 2015, 6:34 p.m. UTC 
This adds an option for the Qualcomm server parts, qdf24xx, just
optimizing like a cortex-a57 for now, same as how the initial Samsung
exynos-m1 support worked.

This was tested with armv8 and aarch64 bootstraps and make check.

I had to disable the cortex-a57 fma steering pass in the aarch64 port
while testing the patch.  A bootstrap for aarch64 configured
--with-cpu=cortex-a57 gives multiple ICEs while building the stage1
libstdc++.  The ICEs are in scan_rtx_reg at regrename.c:1074.  This
looks vaguely similar to PR 66785.

I am also seeing extra make check failures due to ICEs with armv8
bootstrap builds configured --with-cpu=cortex-a57,  I see ICEs in
scan_rtx_reg in regrename, and ICEs in decompose_normal_address in
rtlanal.c.  The arm port doesn't have the fma steering support, which
seems odd, and is maybe a bug, so it isn't clear what is causing this
problem.

I plan to look at these aarch64 and armv8 failures next, including PR
66785.  None of these have anything to do with my patch, as they
trigger for cortex-a57 which is already supported.

Jim

Comments

Jim Wilson Nov. 11, 2015, 7:55 p.m. UTC | #1 
On Wed, Nov 11, 2015 at 10:34 AM, Jim Wilson <jim.wilson@linaro.org> wrote:
> I had to disable the cortex-a57 fma steering pass in the aarch64 port

> while testing the patch.  A bootstrap for aarch64 configured

> --with-cpu=cortex-a57 gives multiple ICEs while building the stage1

> libstdc++.  The ICEs are in scan_rtx_reg at regrename.c:1074.  This

> looks vaguely similar to PR 66785.


It looks like there is already a discussion of this issue in the
"Preferred rename register in regrename pass" thread, though I'm not
sure yet if it is the same issue or a closely related one.

Jim
James Greenhalgh Nov. 12, 2015, 11:42 a.m. UTC | #2 
On Wed, Nov 11, 2015 at 10:34:53AM -0800, Jim Wilson wrote:
> This adds an option for the Qualcomm server parts, qdf24xx, just

> optimizing like a cortex-a57 for now, same as how the initial Samsung

> exynos-m1 support worked.

> 

> This was tested with armv8 and aarch64 bootstraps and make check.

> 

> I had to disable the cortex-a57 fma steering pass in the aarch64 port

> while testing the patch.  A bootstrap for aarch64 configured

> --with-cpu=cortex-a57 gives multiple ICEs while building the stage1

> libstdc++.  The ICEs are in scan_rtx_reg at regrename.c:1074.  This

> looks vaguely similar to PR 66785.

> 

> I am also seeing extra make check failures due to ICEs with armv8

> bootstrap builds configured --with-cpu=cortex-a57,  I see ICEs in

> scan_rtx_reg in regrename, and ICEs in decompose_normal_address in

> rtlanal.c.  The arm port doesn't have the fma steering support, which

> seems odd, and is maybe a bug, so it isn't clear what is causing this

> problem.

> 

> I plan to look at these aarch64 and armv8 failures next, including PR

> 66785.  None of these have anything to do with my patch, as they

> trigger for cortex-a57 which is already supported.


The bootstrap bugs should be fixed on trunk as of:

  http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=230149

The AArch64 parts are OK, but the ARM parts look to be missing a hunk to
gcc/config/arm/t-aprofile (and I can't approve those anyway).

Thanks,
James


> Index: gcc/ChangeLog

> ===================================================================

> --- gcc/ChangeLog	(revision 230118)

> +++ gcc/ChangeLog	(working copy)

> @@ -1,3 +1,13 @@

> +2015-11-10  Jim Wilson  <jim.wilson@linaro.org>

> +

> +	* config/aarch64/aarch64-cores.def (qdf24xx): New.

> +	* config/aarch64/aarch64-tune.md: Regenerated.

> +	* config/arm/arm-cores.def (qdf24xx): New.

> +	* config/arm/arm-tables.opt, config/arm/arm-tune.md: Regenerated.

> +	* config/arm/bpabi.h (BE8_LINK_SPEC): Add qdf24xx support.

> +	* doc/invoke.texi (AArch64 Options/-mtune): Add "qdf24xx".

> +	(ARM Options/-mtune); Likewise.
diff mbox

Patch

Index: gcc/ChangeLog
===================================================================
--- gcc/ChangeLog	(revision 230118)
+++ gcc/ChangeLog	(working copy)
@@ -1,3 +1,13 @@ 
+2015-11-10  Jim Wilson  <jim.wilson@linaro.org>
+
+	* config/aarch64/aarch64-cores.def (qdf24xx): New.
+	* config/aarch64/aarch64-tune.md: Regenerated.
+	* config/arm/arm-cores.def (qdf24xx): New.
+	* config/arm/arm-tables.opt, config/arm/arm-tune.md: Regenerated.
+	* config/arm/bpabi.h (BE8_LINK_SPEC): Add qdf24xx support.
+	* doc/invoke.texi (AArch64 Options/-mtune): Add "qdf24xx".
+	(ARM Options/-mtune); Likewise.
+
 2015-11-10  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/i386.c (ix86_print_operand): Remove dead code that
Index: gcc/config/aarch64/aarch64-cores.def
===================================================================
--- gcc/config/aarch64/aarch64-cores.def	(revision 230118)
+++ gcc/config/aarch64/aarch64-cores.def	(working copy)
@@ -44,6 +44,7 @@  AARCH64_CORE("cortex-a53",  cortexa53, cortexa53,
 AARCH64_CORE("cortex-a57",  cortexa57, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07")
 AARCH64_CORE("cortex-a72",  cortexa72, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08")
 AARCH64_CORE("exynos-m1",   exynosm1,  cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa72, "0x53", "0x001")
+AARCH64_CORE("qdf24xx",     qdf24xx,   cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57, "0x51", "0x800")
 AARCH64_CORE("thunderx",    thunderx,  thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  "0x43", "0x0a1")
 AARCH64_CORE("xgene1",      xgene1,    xgene1,    8A,  AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000")
 
Index: gcc/config/aarch64/aarch64-tune.md
===================================================================
--- gcc/config/aarch64/aarch64-tune.md	(revision 230118)
+++ gcc/config/aarch64/aarch64-tune.md	(working copy)
@@ -1,5 +1,5 @@ 
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr "tune"
-	"cortexa53,cortexa57,cortexa72,exynosm1,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
+	"cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
Index: gcc/config/arm/arm-cores.def
===================================================================
--- gcc/config/arm/arm-cores.def	(revision 230118)
+++ gcc/config/arm/arm-cores.def	(working copy)
@@ -169,6 +169,7 @@  ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A,	A
 ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
 ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
 ARM_CORE("exynos-m1",	exynosm1,  cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("qdf24xx",	qdf24xx,   cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
 ARM_CORE("xgene1",      xgene1,    xgene1,      8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A),            xgene1)
 
 /* V8 big.LITTLE implementations */
Index: gcc/config/arm/arm-tables.opt
===================================================================
--- gcc/config/arm/arm-tables.opt	(revision 230118)
+++ gcc/config/arm/arm-tables.opt	(working copy)
@@ -316,6 +316,9 @@  EnumValue
 Enum(processor_type) String(exynos-m1) Value(exynosm1)
 
 EnumValue
+Enum(processor_type) String(qdf24xx) Value(qdf24xx)
+
+EnumValue
 Enum(processor_type) String(xgene1) Value(xgene1)
 
 EnumValue
Index: gcc/config/arm/arm-tune.md
===================================================================
--- gcc/config/arm/arm-tune.md	(revision 230118)
+++ gcc/config/arm/arm-tune.md	(working copy)
@@ -33,6 +33,6 @@ 
 	cortexm7,cortexm4,cortexm3,
 	marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
 	cortexa53,cortexa57,cortexa72,
-	exynosm1,xgene1,cortexa57cortexa53,
-	cortexa72cortexa53"
+	exynosm1,qdf24xx,xgene1,
+	cortexa57cortexa53,cortexa72cortexa53"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
Index: gcc/config/arm/bpabi.h
===================================================================
--- gcc/config/arm/bpabi.h	(revision 230118)
+++ gcc/config/arm/bpabi.h	(working copy)
@@ -74,6 +74,7 @@ 
    |mcpu=cortex-a72					\
    |mcpu=cortex-a72.cortex-a53				\
    |mcpu=exynos-m1                                      \
+   |mcpu=qdf24xx					\
    |mcpu=xgene1                                         \
    |mcpu=cortex-m1.small-multiply                       \
    |mcpu=cortex-m0.small-multiply                       \
@@ -99,6 +100,7 @@ 
    |mcpu=cortex-a72					\
    |mcpu=cortex-a72.cortex-a53				\
    |mcpu=exynos-m1                                      \
+   |mcpu=qdf24xx					\
    |mcpu=xgene1                                         \
    |mcpu=cortex-m1.small-multiply                       \
    |mcpu=cortex-m0.small-multiply                       \
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 230118)
+++ gcc/doc/invoke.texi	(working copy)
@@ -12575,7 +12575,7 @@  processors implementing the target architecture.
 Specify the name of the target processor for which GCC should tune the
 performance of the code.  Permissible values for this option are:
 @samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
-@samp{exynos-m1}, @samp{thunderx}, @samp{xgene1}.
+@samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx}, @samp{xgene1}.
 
 Additionally, this option can specify that GCC should tune the performance
 of the code for a big.LITTLE system.  Permissible values for this
@@ -13495,6 +13495,7 @@  Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{cortex-m0.small-multiply},
 @samp{cortex-m0plus.small-multiply},
 @samp{exynos-m1},
+@samp{qdf24xx},
 @samp{marvell-pj4},
 @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
 @samp{fa526}, @samp{fa626},