From patchwork Wed Dec 14 04:31:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Turquette X-Patchwork-Id: 5666 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 7528C23E01 for ; Wed, 14 Dec 2011 04:34:49 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 6BA4EA18265 for ; Wed, 14 Dec 2011 04:34:49 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id k10so61148eaa.11 for ; Tue, 13 Dec 2011 20:34:49 -0800 (PST) Received: by 10.205.120.135 with SMTP id fy7mr207708bkc.54.1323837289204; Tue, 13 Dec 2011 20:34:49 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs101261bkc; Tue, 13 Dec 2011 20:34:48 -0800 (PST) Received: by 10.68.189.168 with SMTP id gj8mr1067335pbc.82.1323837286825; Tue, 13 Dec 2011 20:34:46 -0800 (PST) Received: from na3sys009aog110.obsmtp.com ([74.125.149.203]) by mx.google.com with SMTP id mj2si5079556pbc.165.2011.12.13.20.34.42 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 13 Dec 2011 20:34:46 -0800 (PST) Received-SPF: pass (google.com: domain of mturquette@ti.com designates 74.125.149.203 as permitted sender) client-ip=74.125.149.203; Authentication-Results: mx.google.com; spf=pass (google.com: domain of mturquette@ti.com designates 74.125.149.203 as permitted sender) smtp.mail=mturquette@ti.com Received: from mail-gy0-f172.google.com ([209.85.160.172]) (using TLSv1) by na3sys009aob110.postini.com ([74.125.148.12]) with SMTP ID DSNKTugnYghV27KHK+SIyAgcxmFerCsgsc1o@postini.com; Tue, 13 Dec 2011 20:34:46 PST Received: by ghrr16 with SMTP id r16so328944ghr.3 for ; Tue, 13 Dec 2011 20:34:42 -0800 (PST) Received: by 10.236.201.194 with SMTP id b42mr9001480yho.32.1323837281932; Tue, 13 Dec 2011 20:34:41 -0800 (PST) Received: from localhost.localdomain (dragon.ti.com. [192.94.94.33]) by mx.google.com with ESMTPS id v48sm2145601yhk.6.2011.12.13.20.34.38 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 13 Dec 2011 20:34:41 -0800 (PST) From: Mike Turquette To: linux@arm.linux.org.uk Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, khilman@ti.com, tony@atomide.com, b-cousson@ti.com, rnayak@ti.com, jeremy.kerr@canonical.com, paul@pwsan.com, broonie@opensource.wolfsonmicro.com, tglx@linutronix.de, linus.walleij@stericsson.com, amit.kucheria@linaro.org, dsaxena@linaro.org, patches@linaro.org, linaro-dev@lists.linaro.org, grant.likely@secretlab.ca, sboyd@quicinc.com, shawn.guo@freescale.com, skannan@quicinc.com, magnus.damm@gmail.com, arnd.bergmann@linaro.org, eric.miao@linaro.org, richard.zhao@linaro.org, mturquette@linaro.org, mturquette@ti.com, andrew@lunn.ch Subject: [PATCH 3/6] HACK: omap: clk: add mpu_periphclk clk node Date: Tue, 13 Dec 2011 20:31:25 -0800 Message-Id: <1323837088-2469-4-git-send-email-mturquette@ti.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323837088-2469-1-git-send-email-mturquette@ti.com> References: <1323837088-2469-1-git-send-email-mturquette@ti.com> From: Mike Turquette The ARM periphclk drives various peripherals for the MPU including the TWD and local timers. This patch creates the missing clk tree data to represent this relationship: dpll_mpu_ck | dpll_mpu_m2_ck (divide by 1) | mpu_clk (divide by 1) | mpu_periphclk (divide by 2) This patch is based on Santosh Shilimkar's original version: http://article.gmane.org/gmane.linux.ports.arm.omap/64936 Not-signed-off-by: Mike Turquette --- arch/arm/mach-omap2/clock44xx_data.c | 37 +++++++++++++++++++++++++++++++++- 1 files changed, 36 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 33249b3..6c6d0fb 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1035,7 +1035,7 @@ static const struct clksel dpll_mpu_m2_div[] = { static const struct clk_hw_ops dpll_mpu_m2_ck_ops = { .recalc_rate = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, + .round_rate = &omap2_passthrough_round_rate, .set_rate = &omap2_clksel_set_rate, .get_parent = &omap2_get_parent_fixed, }; @@ -1043,6 +1043,7 @@ static const struct clk_hw_ops dpll_mpu_m2_ck_ops = { static struct clk_hw_omap dpll_mpu_m2_ck_hw = { .clk = { .name = "dpll_mpu_m2_ck", + .flags = CLK_PARENT_SET_RATE, .ops = &dpll_mpu_m2_ck_ops, }, .fixed_parent = &dpll_mpu_ck_hw.clk, @@ -1053,6 +1054,38 @@ static struct clk_hw_omap dpll_mpu_m2_ck_hw = { .deny_idle = &omap4_dpllmx_deny_gatectrl, }; +static const struct clk_hw_ops mpu_clk_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .round_rate = &omap2_passthrough_round_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap mpu_clk_hw = { + .clk = { + .name = "mpu_clk", + .flags = CLK_PARENT_SET_RATE, + .ops = &mpu_clk_ops, + }, + .fixed_parent = &dpll_mpu_m2_ck_hw.clk, + .fixed_div = 1, +}; + +static const struct clk_hw_ops mpu_periphclk_ops = { + .recalc_rate = &omap_fixed_divisor_recalc, + .round_rate = &omap2_passthrough_round_rate, + .get_parent = &omap2_get_parent_fixed, +}; + +static struct clk_hw_omap mpu_periphclk_hw = { + .clk = { + .name = "mpu_periphclk", + .flags = CLK_PARENT_SET_RATE, + .ops = &mpu_periphclk_ops, + }, + .fixed_parent = &mpu_clk_hw.clk, + .fixed_div = 2, +}; + static const struct clk_hw_ops per_hs_clk_div_ck_ops = { .recalc_rate = &omap_fixed_divisor_recalc, .get_parent = &omap2_get_parent_fixed, @@ -4071,6 +4104,8 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck_hw.clk, CK_443X), CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck_hw.clk, CK_443X), CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck_hw.clk, CK_443X), + CLK(NULL, "mpu_clk", &mpu_clk_hw.clk, CK_443X), + CLK("smp_twd", NULL, &mpu_periphclk_hw.clk, CK_443X), CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck_hw.clk, CK_443X), CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck_hw.clk, CK_443X), CLK(NULL, "dpll_per_ck", &dpll_per_ck_hw.clk, CK_443X),