diff mbox series

[2/7] clk: qcom: ipq8074: disable USB GDSC-s SW_COLLAPSE

Message ID 20220425182249.2753690-2-robimarko@gmail.com
State New
Headers show
Series [1/7] clk: qcom: ipq8074: fix NSS core PLL-s | expand

Commit Message

Robert Marko April 25, 2022, 6:22 p.m. UTC
Like in IPQ6018 Qualcomm intentionally disables the SW_COLLAPSE on the USB
GDSC-s in the downstream 5.4 kernel.

This could potentially be better handled by utilizing the GDSC driver, but
I am not familiar with it nor do I have datasheets.

Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 drivers/clk/qcom/gcc-ipq8074.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Bjorn Andersson May 6, 2022, 3:33 a.m. UTC | #1
On Mon 25 Apr 13:22 CDT 2022, Robert Marko wrote:

> Like in IPQ6018 Qualcomm intentionally disables the SW_COLLAPSE on the USB
> GDSC-s in the downstream 5.4 kernel.
> 
> This could potentially be better handled by utilizing the GDSC driver, but
> I am not familiar with it nor do I have datasheets.

Could you please give it a try before we pick this up?
Look at e.g. drivers/clk/qcom/gcc-sdm845.c how usb30_prim_gdsc and
usb30_sec_gdsc are defined, the offsets in specified in .gdscr should be
the same offsets you give below.

Then you specify an array of struct gdsc *, associating the two gdscs
you have specified to some identifier (USB30_PRIM_GDSC and
USB30_SEC_GDSC is used in sdm845) and reference this list as .gdscs and
num_gdscs in the gcc_ipq8074_desc.

The last part is to tie the USB controllers to the two GDSCs, this is
done by simply specifying:

	power-domains = <&gcc USB30_PRIM_GDSC>;

and USB30_SEC_GDSC, in the two USB nodes in DeviceTree. SW_COLLAPSE will
be toggled by the PM state of the USB driver, like it's done on e.g.
sdm845.

Regards,
Bjorn

> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
>  drivers/clk/qcom/gcc-ipq8074.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
> index 2ebd1462db78..65249a03a672 100644
> --- a/drivers/clk/qcom/gcc-ipq8074.c
> +++ b/drivers/clk/qcom/gcc-ipq8074.c
> @@ -4806,6 +4806,11 @@ static int gcc_ipq8074_probe(struct platform_device *pdev)
>  	if (IS_ERR(regmap))
>  		return PTR_ERR(regmap);
>  
> +	/* Disable SW_COLLAPSE for USB0 GDSCR */
> +	regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
> +	/* Disable SW_COLLAPSE for USB1 GDSCR */
> +	regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
> +
>  	clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
>  	clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
>  				&nss_crypto_pll_config);
> -- 
> 2.35.1
>
Robert Marko May 6, 2022, 9:54 p.m. UTC | #2
On Fri, 6 May 2022 at 05:33, Bjorn Andersson <bjorn.andersson@linaro.org> wrote:
>
> On Mon 25 Apr 13:22 CDT 2022, Robert Marko wrote:
>
> > Like in IPQ6018 Qualcomm intentionally disables the SW_COLLAPSE on the USB
> > GDSC-s in the downstream 5.4 kernel.
> >
> > This could potentially be better handled by utilizing the GDSC driver, but
> > I am not familiar with it nor do I have datasheets.
>
> Could you please give it a try before we pick this up?
> Look at e.g. drivers/clk/qcom/gcc-sdm845.c how usb30_prim_gdsc and
> usb30_sec_gdsc are defined, the offsets in specified in .gdscr should be
> the same offsets you give below.
>
> Then you specify an array of struct gdsc *, associating the two gdscs
> you have specified to some identifier (USB30_PRIM_GDSC and
> USB30_SEC_GDSC is used in sdm845) and reference this list as .gdscs and
> num_gdscs in the gcc_ipq8074_desc.
>
> The last part is to tie the USB controllers to the two GDSCs, this is
> done by simply specifying:
>
>         power-domains = <&gcc USB30_PRIM_GDSC>;
>
> and USB30_SEC_GDSC, in the two USB nodes in DeviceTree. SW_COLLAPSE will
> be toggled by the PM state of the USB driver, like it's done on e.g.
> sdm845.

Hi Bjorn, thanks for the tips, it makes more sense now.
The only thing I am not sure about are the feature flags for these GDSCs,
how to figure out which ones are correct as I dont have datasheets and QCA
does not use GDSCs in the downstream kernel?
POLL_CFG_GDSCR will cause the GDSC not to get enabled, while VOTABLE
seems to work.

Regards,
Robert

>
> Regards,
> Bjorn
>
> >
> > Signed-off-by: Robert Marko <robimarko@gmail.com>
> > ---
> >  drivers/clk/qcom/gcc-ipq8074.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
> > index 2ebd1462db78..65249a03a672 100644
> > --- a/drivers/clk/qcom/gcc-ipq8074.c
> > +++ b/drivers/clk/qcom/gcc-ipq8074.c
> > @@ -4806,6 +4806,11 @@ static int gcc_ipq8074_probe(struct platform_device *pdev)
> >       if (IS_ERR(regmap))
> >               return PTR_ERR(regmap);
> >
> > +     /* Disable SW_COLLAPSE for USB0 GDSCR */
> > +     regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
> > +     /* Disable SW_COLLAPSE for USB1 GDSCR */
> > +     regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
> > +
> >       clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
> >       clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
> >                               &nss_crypto_pll_config);
> > --
> > 2.35.1
> >
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 2ebd1462db78..65249a03a672 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4806,6 +4806,11 @@  static int gcc_ipq8074_probe(struct platform_device *pdev)
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
+	/* Disable SW_COLLAPSE for USB0 GDSCR */
+	regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
+	/* Disable SW_COLLAPSE for USB1 GDSCR */
+	regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
+
 	clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
 	clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
 				&nss_crypto_pll_config);