diff mbox series

[3/4] spi: synquacer: DMSTART bit must not be set while transferring

Message ID 20220517084139.6986-4-masahisa.kojima@linaro.org
State Accepted
Commit de9f2c9c2ed8ee4ffadc3909a46c17888fed619f
Headers show
Series spi-synquacer fixes and improvement | expand

Commit Message

Masahisa Kojima May 17, 2022, 8:41 a.m. UTC 
DMSTART bit must not be set while there is active transfer.
This commit sets the DMSTART bit only when the transfer begins.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
---
 drivers/spi/spi-synquacer.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

Comments

Jassi Brar May 18, 2022, 3:43 a.m. UTC | #1 
On Tue, 17 May 2022 at 03:41, Masahisa Kojima
<masahisa.kojima@linaro.org> wrote:
>
> DMSTART bit must not be set while there is active transfer.
> This commit sets the DMSTART bit only when the transfer begins.
>
> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
> ---
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Tom Rini June 10, 2022, 9:40 p.m. UTC | #2 
On Tue, May 17, 2022 at 05:41:38PM +0900, Masahisa Kojima wrote:

> DMSTART bit must not be set while there is active transfer.
> This commit sets the DMSTART bit only when the transfer begins.
> 
> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>

Applied to u-boot/next, thanks!
diff mbox series

Patch

diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index f1422cf893..5e1b3aedc7 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -330,9 +330,11 @@  static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	writel(~0, priv->base + RXC);
 
 	/* Trigger */
-	val = readl(priv->base + DMSTART);
-	val |= BIT(TRIGGER);
-	writel(val, priv->base + DMSTART);
+	if (flags & SPI_XFER_BEGIN) {
+		val = readl(priv->base + DMSTART);
+		val |= BIT(TRIGGER);
+		writel(val, priv->base + DMSTART);
+	}
 
 	while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
 		if (priv->rx_words)